lp header

Agnisys, Inc. announced the release of IDesignSpecTM (IDS)

Lowell, MA, May 1st 2009

Agnisys, Inc. a startup dedicated to automating SoC Design and Verification methodology, today announced the release of IDesignSpecTM(IDS), a new tool for Register Management and Automation for hardware designs. IDS decreases the time and effort to specify hardware registers and automates the generation of data required by RTL design, verification, diagnostic, software and lab debug. This reduces development cost while improving quality and time to market. IDS is targeted at companies developing IPs, SoCs, ASICs and FPGAs.

IDesignSpecTM is available for limited time evaluations. For qualified non-profits, Agnisys is making the tool available for free.

Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.

streamline semiconductor design verification validation documentation