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Agnisys Demonstrates Solutions For RISC-V System Development

Milpitas, Calif., December 04, 2019 – Agnisys, Inc., will present its customer proven SoC design and intellectual property (IP) solutions at the RISC-V Summit, December 10 – 12, 2019. The company will focus on showcasing how IDesignSpec along with ARV and ISequenceSpec enable software, hardware, verification and validation engineers to accelerate their IP/SoC development cycle and mitigate the risk for first pass silicon.

The RISC-V summit in San Jose brings together RISC-V technology users, developers, and industry experts for three days of networking, sharing best practices on critical design and verification issues, discovering new techniques for designing advanced silicon, SoCs, and systems based on the RISC-V processor.

At the summit, Agnisys will showcase a flow using Agnisys software tools, wherein hardware and software teams can collaborate efficiently to easily create RISC-V based IPs/SoCs targeting both ASICs and FPGAs. Using IDesignSpec along with ARV, they will demonstrate how design teams can automatically generate the RTL from a golden register specification along with C-headers, UVM verification environment and virtual prototyping models for a variety of platforms and bus fabrics such as TileLink, AMBA® AXI, AMBA® AHB, AMBA® APB, Avalon® and custom.

Agnisys will also demonstrate the ease with which design teams can automate their test environments for simulation, firmware development, emulation and post-silicon validation by creating standard and custom test sequences using either GUI or text. Development teams can use ARV to create automatic tests for IPs and use ISequenceSpec to generate custom sequences. Software teams can leverage the sequences to validate the hardware thereby identifying potential system issues earlier in the product life cycle.

In addition, Agnisys also provides a rich standard library of completely customizable peripheral IPs such as GPIO, I2C, Timer, PIC, DMA, PWM etc., which designers can use to accelerate their SoC development.

December 10-12, 2019

RISC-V Summit, San Jose Convention Center – San Jose, CA.  For more information and to register.

Media contact for Agnisys:
Phone: +1 855-VERIFYY
Email: marcom@agnisys.com

Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.

streamline semiconductor design verification validation documentation