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EDACafe Industry prediction for 2023 - Agnisys

Sanjay2Interview of Anupam Bakshi by Sanjay Gangal, EDA Cafe
Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999. 

What are your top semiconductor predictions for 2023?

Automatic generation of the RTL design will continue beyond the hardware-software interface (HSI) layer. It will encompass a whole custom IP, enabling users to generate much of their design directly from their specifications. The generation process will include high-quality documentation suitable for inclusion in user manuals.

Anupam-PhotoThe range of available standard IP will continue to grow, with many configuration and customization options. Automated integration of both standard and custom IP to build subsystems and a complete SoC will expand to include all aspects of SoC creation. The generated RTL designs will include custom and standard bus interfaces, functional safety mechanisms to detect and correct errors, and clock domain crossing (CDC) logic.

Automatic verification will continue to include not only testbench generation but test generation as well, plus generation of assertions for use in both simulation and formal verification. Generated C/C++ code will be used by programmers to develop and test their embedded code and device drivers.

Finally, the RISC-V movement will continue moving along briskly with greater need of automated solutions for IP and system level modeling.

Read the article on EDACafe

Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.

streamline semiconductor design verification validation documentation