Creation of the UVM test environment from scratch takes extensive time and meticulous attention. While UVM provides standard register and memory tests such as reset, bit_bash, and access, they only provide ~60% functional coverage out of the box. The user has to manually put in the effort to cover the remaining 40%. Automation that provides 100% coverage is key to verification success as IPs and SoCs grow in complexity.
Based on the register specification, Automatic Register Verification (ARV™) generates the complete UVM testbench: bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences, as well as the Makefile and Verification Plan. The UVM testbench is fully connected to the UVM Register Model and DUT, providing you with a push-button verification.
Sequences are automatically generated for various types of register behavior. These sequences are called out by a virtual sequence based on the access type of the fields. You can generate First-Level Sequences for the fields, Register-Level Sequences for registers and positive/negative sequences for Special Registers.
Verification via Simulation and Formal
Verification can be done using complementary verification methodologies. The generated files include “Makefiles” for the industry popular simulations and formal tools. In addition to direct and constrained random simulation test-cases, the entire verification process can be further improved by formally verifying IPs with the slave interface, reducing simulation runs and overheads involved in creating block-level test-benches.
Verification Plan and Coverage Report
The generated graphical report includes a Verification Plan showing the complete summary of the coverage results and test status. The hierarchy of the IP along with functional coverage is displayed in HTML format. The data is depicted with various colors to easily get the percentage of the pass and failure of the coverage. The Zoom functionality helps you focus on a specific component and its internal hierarchy.
ARV-Sim™ is a complete register verification solution that integrates with Synopsys VCS®, Cadence Incisive® and Mentor Questa® simulators. ARV-Sim automatically generates the complete package including bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences required for System Verilog (SV), Universal Verification Methodology (UVM) testing. It creates the simulator make-files to completely automate the verification process. This approach eliminates the lengthy and error prone UVM test bench and sequence creation process. ARV-Sim provides the positive and negative sequences automatically – not just the test bench but also the actual test sequences that stimulates the hardware to ensure that the implementation is correct.
ARV-Sim™, ARV-Formal™ Availability
ARV-Formal™ and ARV-Sim™ are add-on products to IDesignSpec. Engineering teams may request an ARV-Formal or ARV-Sim evaluation by completing this website form. Also available is a detailed product datasheet and whitepaper.
ARV-Sim™ and ARV-Formal™ are immediately available on Windows and Linux (Redhat and Ubuntu).