IDS-FPGA: Xilinx
Introduction
IDesignSpec (IDS) suite of products can seamlessly integrate into your Vivado projects allowing for faster turnaround times. IDS can generate the RTL for your addressable register which can then be easily packaged as an IP and ready to be used in your design. IDS also offers support to create mirror blocks of IPs and creation of automatic and custom sequences to program your design.
IDS-NextGen
IDS-NextGen (IDS-NG) is Agnisys’ cross platform GUI that allows users to create register specifications and generate a variety of collaterals including synthesizable RTL, UVM RAL, headers, documentation and programmable sequences.
IDS-FPGA
IDS-FPGA leverages the TCL library from Vivado to easily integrate your IDS-NG project into your FPGA design.
Vivado has the capability to create buttons that can be tied to other programs or scripts. Using this functionality you can create a button to link our Vivado project with a corresponding IDS-NG project.
Once you create your design in IDS-NG in the configuration menu you have the option to generate outputs for your specific FPGA targeted board. Along with generating your RTL this option will create the following files:
- <file_name>.tcl
- ids_mirror_block.v
- ids_connect.tcl
When you run the <file_name>.tcl script in Vivado it will import all generated files to your current project and package them as an IP that can be used in your block design.
The ids_mirror_block is a 1-to-1 mirror of your generated block. It will create a skeleton block that has the same number of input and output ports of your generated block and allow you to implement your own functionality.
The ids_connect.tcl script will automatically connect the ports between your generated block and the mirror block.
Once the generated scripts are run you can see that the design is automatically imported and the connection between blocks are created.
After you have your design completed you can run synthesis, implementation, and generate the bitstream.
IDS-Validate
A key feature of IDS-NG is its variety of different views/templates. One of these views, the sequence template , allows you to create programmable sequences using the information captured in your register template along with APIs for reads, writes, loops, and other conditions. The sequence template also has additional features like auto for property and register names and formatting.
