Chip Development Shift Left Starts with the Specifications
American statesman Benjamin Franklin is famously quoted as saying “in this world, nothing is certain except death and taxes.” To this, we can add “bigger and more complex chips.” Today’s system-on-chip (SoC) designs have billions of circuit elements and incredibly sophisticated architectures with high degrees of parallelism. Such massive designs are required to tackle the toughest electronics applications, including high-performance computing (HPC) and artificial intelligence (AI).
Challenges of SoC Development
One direct consequence of large and complex chips is a longer development cycle. Every step of the process—architecture, register-transfer-level (RTL) design, verification, programming, validation, layout, signoff, bringup, and documentation—takes longer than previous generations. Some argue that design time grows less than linearly due to a great deal of reuse. However, other steps such as verification grow exponentially from one generation to the next.
You might think that simply adding more engineers to the development teams would pull schedules back in. The publication of The Mythical Man-Month nearly fifty years ago showed that adding human resources to projects may actually prolong development time due to training and communication overhead. Moreover, even if more engineers could help, it is very hard to find and hire experts in all the fields involved in the SoC development process.
The consequences of this dilemma are clear: longer schedules mean higher development costs and delayed time to market (TTM). These effects reduce the potential profitability and lifespan of semiconductor products and the systems built upon them. Even worse, late products may miss the market entirely, especially when competitors have been able to move more quickly. At that point, sunk development costs with no payback can severely injure or even kill companies.
The Importance of Shift Left
Recognizing the need for their SoC customers to accomplish more in less time, electronic design automation (EDA) companies have invested in innovative solutions. The term “shift left” of development projects and schedules is commonly used to describe one of the major purposes of EDA tools. The goals are clear: shrink the time required for development tasks, enable these tasks to start earlier in the development cycle, and reduce the number of task iterations.
It’s easy to state these goals, but it’s a lot harder to accomplish them. Reducing the time to complete individual tasks is perhaps the easiest, since improved tool speed and increased parallelism help a great deal. Moving tasks earlier in the development process is considerably harder, since a shift to a higher level of abstraction is usually required. For example, high-level architectural models and virtual prototypes have allowed some aspects of verification and validation to happen before RTL design.
Reducing iterations is also very challenging. Sometimes this happens as the result of moving tasks earlier. For example, running trial layouts as part of the logic synthesis process leads to fewer full-chip place-and-route runs. However, some iterations are the result of design evolution over the course of SoC projects. Design specifications change many times, and every change has ripple effects on most or all development tasks.
Shift Left through Specification Automation
The best way to move your development tasks earlier and minimize iterations is to automate as many of the development tasks as possible. Auto-generating many types of files used in development from the design specifications avoids a great deal of manual coding, saving time and resources. Such generated files are correct by construction since they come directly from the specifications. This reduces the time for checking, verification, and validation by eliminating the long debug cycles to find and fix manual coding errors. This result is a significant shift left in your project schedules.
Automatic generation of files also eliminates the need for manual iterations of most development tasks. When specifications change due to evolving market requirements or technology, all files are simply regenerated. This shifts your development further left and saves a great deal of resources. In addition, auto-generation ensures that all development teams always remain synchronized. This eliminates a whole class of bugs due to inconsistent designs, verification environments, and software.
This whole process is known as specification automation. It relies on two key capabilities: executable golden specifications that enable auto-generation and the tools that actually generate the files. While it is not practical today to generate all the hardware and software for an SoC automatically, many files critical to the development process can be generated directly from executable specifications and regenerated whenever these specifications change.
The best way to move your development tasks earlier and minimize iterations is to automate as many of the development tasks as possible. Auto-generating many types of files used in development from the design specifications avoids a great deal of manual coding, saving time and resources. Such generated files are correct by construction since they come directly from the specifications. This reduces the time for checking, verification, and validation by eliminating the long debug cycles to find and fix manual coding errors. This result is a significant shift left in your project schedules.
Automatic generation of files also eliminates the need for manual iterations of most development tasks. When specifications change due to evolving market requirements or technology, all files are simply regenerated. This shifts your development further left and saves a great deal of resources. In addition, auto-generation ensures that all development teams always remain synchronized. This eliminates a whole class of bugs due to inconsistent designs, verification environments, and software.
This whole process is known as specification automation. It relies on two key capabilities: executable golden specifications that enable auto-generation and the tools that actually generate the files. While it is not practical today to generate all the hardware and software for an SoC automatically, many files critical to the development process can be generated directly from executable specifications and regenerated whenever these specifications change.
The Agnisys Solution
Agnisys is a pioneer in specification automation, with thousands of users who have taped out successful SoC projects over many years. The Agnisys IDesignSpec™ Suite of EDA tools fully automates the process of generating many kinds of development files from a wide variety of standard specification formats and intuitive graphical editors.
The generated files include:
- RTL designs, Universal Verification Methodology (UVM) models and tests, and high-quality documentation for programmable registers and memories
- RTL designs for standard bus interfaces, clock-domain-crossing (CDC) logic, functional safety mechanisms, and common design structure such as finite state machines (FSMs)
- RTL designs and formal properties for block interconnects, bug bridges, and bus aggregators
- UVM tests, C/C++ firmware tests, and pre-silicon verification environments for complex register programming sequences
- C/C++ firmware and driver code for post-silicon validation in the bringup lab.