AUGER: Celebrating Our Users
February 12, 2021

AUGER: Celebrating Our Users

Explore the vital role of users in the EDA industry and Agnisys' commitment to their needs. Join us at AUGER for insights and collaboration.

Repurposing von Neumann Architecture with SRAM-based Register Files
August 11, 2019

Repurposing von Neumann Architecture with SRAM-based Register File

By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades.

Not your Average UVM Testbench Generator
May 20, 2019

Not your Average UVM Testbench Generator – Unveiling at DAC 2019

By Louie De Luna, Agnisys Chief Product Evangelist Being so immersed in the work & technology, it’s easy to forget where we are in this tech revolution.

Setting the Stage for the Next Abstraction
March 26, 2019

Setting the Stage for the Next Abstraction

Using abstraction, designers are able to focus on the high-level design & tests while the tools took care of the automation at the low-level.

Register Automation using Machine Learning
February 17, 2019

Register Automation using Machine Learning

By Louie De Luna, Agnisys Director of Sales and Marketing Right after Google’s AlphaGo system defeated a human Go world champion in 2015. Visit now.

It’s All In The Sequence
May 27, 2016

It’s All In The Sequence

Innovative Design Automation Tools: Streamline complex sequences for SoCs, ensuring precision and efficiency. Learn from Apollo 13's lesson.

Making Way For Register Specification Software
May 5, 2016

Making Way For Register Specification Software

Optimize semiconductor design with register specification software, streamlining development processes. Enhance efficiency and quality.

The Ultimate Shift Left
April 11, 2016

The Ultimate Shift Left

Einstein's wisdom meets semiconductor innovation: Shift left with specification-driven design for flawless results. Explore Agnisys' solutions.

2015 Year End review
December 30, 2015

2015 Year End review – DV Challenges

Agnisys reflects on a successful 2015, highlighting partnerships, events, and product innovations in the semiconductor industry.

Does UVM sometimes make you feel stupid?
September 21, 2015

Does UVM sometimes make you feel stupid?

Explore UVM complexities and solutions on Agnisys' blog. Don't let UVM make you feel stumped; find clarity and insights here.

IDesignSpec generated IP
July 22, 2015

Questa® VIP validates IDesignSpec generated IP

Discover how Questa VIP (QVIP) from Mentor Graphics simplifies AMBA AXI4Lite bus protocol verification, saving time and ensuring high-quality .

DVCON 2014
February 5, 2014

DVCON 2014: Strong Focus on both, Design & Verification

DVCON 2014: Discover the dynamic blend of design and verification trends at this year's conference. Stay updated!

Begin Initialization Sequence
December 7, 2012

Begin Initialization Sequence – 10, 9, 8, …

Launching new capability to specify Sequences in IDesignSpec