News Articles
AUGER: Celebrating Our Users
Explore the vital role of users in the EDA industry and Agnisys' commitment to their needs. Join us at AUGER for insights and collaboration.
Repurposing von Neumann Architecture with SRAM-based Register File
By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades.
Not your Average UVM Testbench Generator – Unveiling at DAC 2019
By Louie De Luna, Agnisys Chief Product Evangelist Being so immersed in the work & technology, it’s easy to forget where we are in this tech revolution.
Most Popular Posts
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Not your Average UVM Testbench Generator – Unveiling at DAC 2019 -
Setting the Stage for the Next Abstraction -
Register Automation using Machine Learning -
Repurposing von Neumann Architecture with SRAM-based Register File -
Making Way For Register Specification Software -
Questa® VIP validates IDesignSpec generated IP
Setting the Stage for the Next Abstraction
Using abstraction, designers are able to focus on the high-level design & tests while the tools took care of the automation at the low-level.
Register Automation using Machine Learning
By Louie De Luna, Agnisys Director of Sales and Marketing Right after Google’s AlphaGo system defeated a human Go world champion in 2015. Visit now.
It’s All In The Sequence
Innovative Design Automation Tools: Streamline complex sequences for SoCs, ensuring precision and efficiency. Learn from Apollo 13's lesson.
Making Way For Register Specification Software
Optimize semiconductor design with register specification software, streamlining development processes. Enhance efficiency and quality.
The Ultimate Shift Left
Einstein's wisdom meets semiconductor innovation: Shift left with specification-driven design for flawless results. Explore Agnisys' solutions.
2015 Year End review – DV Challenges
Agnisys reflects on a successful 2015, highlighting partnerships, events, and product innovations in the semiconductor industry.
Does UVM sometimes make you feel stupid?
Explore UVM complexities and solutions on Agnisys' blog. Don't let UVM make you feel stumped; find clarity and insights here.
Questa® VIP validates IDesignSpec generated IP
Discover how Questa VIP (QVIP) from Mentor Graphics simplifies AMBA AXI4Lite bus protocol verification, saving time and ensuring high-quality .
DVCON 2014: Strong Focus on both, Design & Verification
DVCON 2014: Discover the dynamic blend of design and verification trends at this year's conference. Stay updated!
Begin Initialization Sequence – 10, 9, 8, …
Launching new capability to specify Sequences in IDesignSpec