Agnisys and Breker Partner to Generate Portable Stimulus Sequences
Integrated Solution Provides Sequences Reusable From IP-Level Simulation to Post-Silicon Validation
LOWELL, MA and SAN JOSE, CA–(Marketwired – May 24, 2016) – Agnisys and Breker Verification Systems, Inc., today announced availability of an integrated solution for portable test sequences where sequences from the same description are generated for use across all verification platforms, from early-stage simulation to full-chip validation of silicon in the bring-up lab.
ISequenceSpec™ from Agnisys, provider of a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation, enables users to describe programming and test sequences of a device once and generate sequences automatically. It provides a straightforward specification format to describe the sequences and generates the code that ensures synchronization between verification to validation. Users describe initialization, configuration and test sequences and ISequenceSpec automatically generates Universal Verification Methodology (UVM) models and firmware sequences usable throughout the design and verification process.
The Trek™ family of products and apps from Breker, the SoC Verification Company, automatically generates multi-threaded test cases that verify SoC designs design more quickly and more thoroughly. These test cases are reusable from IP to full-chip level, and from simulation to silicon, meeting all requirements for the upcoming Accellera standard on Portable Stimulus. Trek products expand the scope of sequences supported by ISequenceSpec from register and memory read and writes to include sequences involving chip I/O ports and sequences that require parallel execution of multiple threads, scheduling, resource management, and randomization of system-level behavior.
“Traditionally, sequences were hand-written and not portable,” says Anupam Bakshi, Agnisys’ chief executive officer (CEO). “Automatic generation is a major savings in time and effort since sequences do not have to be manually rewritten for each stage in the development process. With this new combined solution, our mutual customers benefit from truly portable sequences.”
“Our tools are efficient at generating portable, self-checking, multi-threaded test cases from IP blocks to multi-SoC configurations and from simulation to silicon,” remarks Adnan Hamid, CEO of Breker. “The abstract specification enabled by ISequenceSpec provides a library of sequences that we can leverage to provide an industry-leading integrated solution.”
Agnisys and Breker will exhibit at the Design Automation Conference (DAC) from Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.
Availability and Pricing
The new, integrated solution is available today from Agnisys or Breker. Local sales representatives should be contacted for details. Pricing is available upon request.
About Agnisys
Agnisys Inc.has established itself as a leading Electronic Design Automation (EDA) supplier of innovative software to solve complex design and verification problems for system development with certainty. Its products provide a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation. Based on patented technology and intuitive user interfaces, they increase productivity and efficiency while eliminating system design and verification errors. Founded in 2007, Agnisys is based in Lowell, Mass., with R&D centers in the United States and India. Phone: (855) 837-4399. Email: sales@agnisys.com .
About Breker Verification Systems
Electronic Design Automation (EDA) software company Breker Verification Systems provides innovative solutions to solve the challenge of complex system-on-chip (SoC) functional verification. Its Trek family of software and applications and its unique SoC scenario-modeling approach are used in production at leading semiconductor companies in the U.S., Europe and Asia. Founded in 2003, Breker is privately held and funded. Daily updates on company activities are available at twitter.com/BrekerSystems. “The Breker Trekker” blog is hosted on EDACafe, available at www10.edacafe.com/blogs/thebrekertrekker. Corporate headquarters: 1879 Lundy Ave., Suite 126, San Jose, Calif. 95131. Telephone: (650) 336-8872. Email: info@brekersystems.com. Website: www.brekersystems.com.
Agnisys acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Trek, TrekUVM, TrekSoC, TrekSoC-Si, TrekApp, TrekBox and SoC Scenario Modeling are trademarks of Breker Verification System, Inc. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.
Contact:
For more information, contact:
Nanette Collins
Public Relations for Agnisys
(617) 437-1822
nanette@nvc.com
Tom Anderson
Breker Verification Systems, Inc.
(408) 823-9075
toma@brekersystems.com
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.
