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Agnisys Presents ISequenceSpec Sequence Generator at DVCon India 2019

Bangalore, India – September 11, 2019 – Agnisys, Inc., the leading EDA provider of the industry’s most comprehensive solution for Design and Verification of SoC Hardware/Software Interface (HSI), to present the latest release of ISequenceSpec™ – Sequence Generator for Custom IPs at DVCon India 2019  in Bangalore, India on September 25-26, 2019. The newest release of ISequenceSpec facilitates the creation of hierarchical and parallel sequences in either Python text-based or spreadsheet environment, and simplifies vertical reuse of the sequences from IP to subsystem and system-level.

The secret sauce or differentiator of today’s SoCs is typically implemented in the custom hardware, whereas long and complex sequences must be created for the verification and validation of its functionality.  Traditionally, SoC groups create UVM sequences for simulation, C code for firmware tests and CSV for post-silicon validation. A huge amount of  time and effort is required to create these sequences in multiple formats, but that can be significantly improved by using a sequence generator.

“The system architect can capture the sequences in pseudo-code and the code generator can output the sequences in the target language,” said Anupam Bakshi, Founder/CEO. “This is a golden-spec methodology for sequences which synchronizes all SoC groups to work and generate code from a single spec eliminating any issues that come up due to miscommunication and disconnect.”

Vertical reuse of the sequences has also been difficult to achieve due to changes in the hardware architecture when moving the tests from IP to subsystem or system level. The level of difficulty is even more compounded because the IP register specs are in various formats (SystemRDL, IP-XACT, CSV, Word, Excel).  Vertical reuse is simplified with the new release of ISequenceSpec.

Additionally, the newest release of ISequenceSpec includes the following main features:

  • Sequence Parallelism – new constructs to enable concurrency are now available including fork_join, fork_join_any and fork_join_none.
  • Constraint Randomization – users are now able to provide randomization using rand() function with or without constraints for register variables and fields.
  • Integration with PSS Tools Cadence® Perspec™ or Mentor® inFact™ – users can write the sequences in the ISequenceSpec spreadsheet or text environment, which in turn generates the output sequence (SystemVerilog or C) mapped to the corresponding PSS action block and exec body.
  • Hierarchical Sequences – users are now able to do sub-sequence calls; structures or arrays can be passed as arguments for subsequence calls.
  • Signals and Interfaces are now supported for reading/writing to DUT
  • New constructs available in C and/or UVM
    • wait, assert, return, time (), concat
    • enums, defines and params

The latest release of ISequenceSpec is now available for download and free evaluation.

About ISequenceSpec

ISequenceSpec provides the environment for capturing the SoC configuration, programming and test sequences in a golden specification. Capture the sequence once in pseudo-code using spreadsheet or text, and generate the required sequences in SystemVerilog for simulation, C for firmware tests, C for emulation and CSV/ASCII for post-silicon validation.  Changes in the golden specification only requires re-generation of the target sequence code. With full access to the register and memory map in SystemRDL, IP-XACT or CSV, users can easily capture test sequences for register read/write and transaction-level messages using advanced constructs including loops, if-else, wait, arguments, constant or in-line functions.

About Agnisys

Agnisys, Inc. is a leading supplier of Electronic Design Automation (EDA) software for solving complex design and verification problems for system development. Its products provide a common specification-driven development flow to describe registers and sequences for System-on-Chip (SoC) and intellectual property (IP) enabling faster design, verification, firmware, and validation. Based on patented technology and intuitive user interfaces, its products increase productivity and efficiency while eliminating system design and verification errors. Founded in 2007, Agnisys is based in Boston, Massachusetts with R&D centers in the United States and India. www.agnisys.com

ISequenceSpec™ is a trademark of Agnisys, Inc. All other trademarks cited herein are the property of their respective owners.

Media Contact: Louie De Luna, Agnisys Director of Marketing/Sales
Phone: +1 855-VERIFYY
Email: marcom@agnisys.com

Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.

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