Agnisys Announces Free Copy of IDesignSpec[TM] & IVerifySpec[TM]
Lowell, MA. May 14, 2013 – Agnisys today announced a free copy of its Executable Design Specification Tool – IDesignSpec[TM] as well as Executable Verification Specification Tool – IVerifySpec[TM]. After meeting with several UVM/OVM users Anupam Bakshi, CEO at Agnisys, Inc. saw the need for an Executable Specification Tool that will enable them to quickly use the UVM/OVM based verification flow. To fill that gap he announced a free version of the tools that can help in automatic verification. To avail this offer, DAC attendees need to visit Agnisys booth # 1543.
Anupam added that it is highly error prone and tedious to create UVM/OVM Registers and Sequence models by hand. With IDesignSpec™ one can simply create the executable specifications in Word, Excel or plain text. Then press a button or enter a command to get any output including UVM/OVM.
IDesignSpec™ enables Architects and Development teams alike to create an executable design specification and generate all types of downstream code from that single specification, such as UVM/OVM Register Model, UVM/OVM Sequences, Verilog/VHDL Synthesizable RTL, C/C++ Headers, System C models, IP-XACT and System RDL models, Documentation and much more. IDesignSpec™ can handle complex Register types and structures. Its versatile TCL API can generate any customized output. The batch version of the tool runs on Linux and Windows and automatically generates outputs from Word or Excel files.
IVerifySpec™ is the tool for creating Executable Specifications for Verification. It enables verification & design team to collaborate and create an executable verification plan. It fits in any verification environment, from any vendor & helps in early identification of verification holes with its sophisticated data collation, aggregation and visualization features.
About Agnisys, Inc.
Agnisys is a pioneer in delivering innovative tools to make your Design Verification team more efficient. Agnisys specializes in creating tools for Executable Specifications. Agnisys has been in the EDA tool industry for more than half a decade and its tools have been trusted by hundreds of users in various companies such as NASA-JPL, Raytheon, Seakr, Exelis, Mercury Computers, Allegro Microsystems, John Deere, Inphi, Amazon Lab 126, Conexant, Intrinsix, Wipro, Compound Photonics, Discretix, Leica GeoSystems, ICRON, Violin Memory, STEC Inc., Volcano Corp, & Mentor Graphics and many more.
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.