A new enhancement has been added to IDesignSpec (IDS) that allows users to create pure bus-forwarding blocks without any register logic. This feature is particularly useful in hierarchical or modular designs where certain blocks serve only to route APB signals downstream without implementing any logic or registers themselves.

To enable this functionality, IDS property bus_forward has been introduced. When applied to a block, this property instructs IDS to skip RTL generation for that block and instead generate only the APB interface. Users can now define blocks as simple pass-through elements in their chip architecture, making the design cleaner and more efficient.

There are two modes for using this property:

1. bus_forward = true
2. bus_forward = “record”

bus_forward = true :

• Whenever a user applies the property “bus_forward=true” on a block, that block does not generate any register logic.
• It generates a flat APB interface with no internal logic

Example:

property bus_forward {type=boolean; component=addrmap;};
property chip {type=boolean; component=addrmap;};
addrmap chip1 {
  chip = true;
  addrmap block1 {
    bus_forward = true;
    reg reg1 {
      field {
        sw=rw;
        hw=rw;
      }f1[31:0]=0x1;
    };
    reg1 reg1;
  };
  addrmap block2 {
    reg reg2 {
      field {
        sw=rw;
        hw=rw;
      }f2[31:0]=0x2;
    };
    reg2 reg2;
  };
  block1 block1;
  block2 block2;
};

Features of bus_forward=true;

• When “bus_forward = true”is set, IDS generates only the APB interface and skips all register logic.
• The bus_forwardproperty can be applied at the block or chip level to control RTL generation.

bus_forward = “record”:

• Bus forward property also supports record-based structures for bus forward signals by setting the value bus_forward = “record”
• It groups related APB signals into a single structured type.
• Reduces the number of individual signal connections between modules.

Example:

property bus_forward {type=string; component=addrmap;};
property chip {type=string; component=addrmap;};
addrmap chip1 {
  chip = true;
  addrmap block1 {
    bus_forward = “record”;
    reg reg1 {
      field {
        sw=rw;
        hw=rw;
      }f1[31:0]=0x1;
    };
    reg1 reg1;
  };
  addrmap block2 {
    reg reg2 {
      field {
        sw=rw;
        hw=rw;
      }f2[31:0]=0x2;
    };
    reg2 reg2;
  };
  block1 block1;
  block2 block2;
};

Features of bus_forward=”record”;

• When “bus_forward = record”is used, IDS generates the APB interface using a single record-based signal structure, making the connection more organized and easier to manage.
• It is especially useful in designs where the same block is repeated multiple times and only requires APB connectivity.

Bus_forward property in case of multiple references.

• Optimized Generation Time and Memory Usage
  By skipping internal register generation, IDS reduces both the time and memory required to produce the output files.
• Cleaner RTL Structure
  The resulting VHDL is more concise and easier to integrate into hierarchical designs.
• Modular and Scalable Design Enablement
  Supports hierarchical systems where not all blocks require register functionality.
• Record-Based Interface Option
  Using VHDL records makes the bus interface cleaner, easier to connect, and more maintainable.
• Customer-Driven Enhancement
  This feature is based on real-world needs and has been implemented to support a specific requirement from Viasat.
• Users can see all expanded instances for each repeated instance of child component in the parent Table of Content along with their indices.