Power and Timing Aware Design: UPF and SDC Support in IDS-Integrate

(Rahul Parashar)

Introduction

Modern SoC designs demand both power efficiency and timing correctness from the very first stages of integration. To address this, IDS-Integrate now supports Unified Power Format (UPF) and Synopsys Design Constraints (SDC) during SoC assembly. This allows designers to bring in IPs along with their associated power and timing information, ensuring smooth integration and reliable implementation.

Role of UPF and SDC in Integration

  • UPF filesdefine the power intent of an IP, including power domains, supply nets, and connectivity. By reading UPF files during integration, IDS-Integrate ensures that hierarchical power structures are preserved and seamlessly rolled up into the SoC-level UPF.
  • SDC filescapture IP-specific timing constraints such as clock definitions, input/output delays, and setup/hold requirements. Integrating these constraints prevents conflicts between multiple IPs and ensures timing closure at the SoC level.

When both UPF and SDC are incorporated, IDS-Integrate is able to automatically generate top-level collaterals (UPF + SDC) that are hierarchy-aware and consistent across all IPs, thereby reducing manual intervention.

Assembly Flow with UPF and SDC

Assmebly IDS-Integrrate

As shown in flow above, During SoC integration, IDS-Integrate reads the RTL of IPs along with their power and timing specifications. It then:

  1. Connects and restructures the hierarchywhile ensuring proper domain mapping.
  2. Merges IP-level UPF filesinto a unified top-level UPF, defining SoC-wide power domains and supply ports.
  3. Consolidates IP-level SDC filesinto a coherent SoC-level constraint set, with clocks and delays aligned to the SoC hierarchy.
  4. Generates final RTL, UPF, and SDC outputsready for downstream implementation and verification.

For example, an APB IP may define its own UPF with create_power_domain, supply ports, and connections, as well as an SDC file with create_clock and input/output delays. IDS-Integrate automatically reads these details and produces a top-level UPF and SDC where the APB, AHB, and AXI IPs are all correctly connected at the SoC wrapper level.

Python Example:

soc_read(search_path=“RTL_Files”,file=[“apb_ip.v”,”ahb_ip.v”,”axi_ip.v”]
soc_read(search_path="UPF_files",file_format="upf",file=["apb_ip.upf","ahb_ip.upf","axi_ip.upf"],block_name=["apb_ip","ahb_ip","axi_ip"])
soc_read(search_path="SDC_files",file_format="sdc",file=["apb_ip.sdc","ahb_ip.sdc","axi_ip.sdc"],block_name=["apb_ip","ahb_ip","axi_ip"])
soc_generate(out=["v","upf","IP-XACT2022","sdc"],dir="ids_leaf_wrapper")

Input UPF File apb_ip.upf

 set_design_top apb_ip
set_scope apb_ip
create_power_domain PD_APB_IP
create_supply_net vdd -domain PD_APB_IP
create_supply_net vss -domain PD_APB_IP
create_supply_port vdd -domain PD_APB_IP -direction in
create_supply_port vss -domain PD_APB_IP -direction in
connect_supply_net vdd -ports vdd
connect_supply_net vss -ports vss

Input SDC file apb_ip.sdc

create_clock -name apb_clk -period 20 -waveform {0.0 10.0 } [get_ports pclk]
# Input delay with respect to apb clock
set_input_delay 2 -max -clock apb_clk [get_ports {signal_b paddr psel pwrite penable pwdata}]
# Output delay with respect to apb clock
set_output_delay 2 -max -clock apb_clk [get_ports {prdata pready pslverr}]

Output TOP Level UPF

load_upf ../../UPF_Input_files/apb_ip.upf
load_upf ../../UPF_Input_files/ahb_ip.upf
load_upf ../../UPF_Input_files/axi_ip.upf
create_power_domain PD_Top
create_supply_net vss -domain PD_Top
create_supply_net vdd -domain PD_Top
create_supply_port vss -domain PD_Top -direction in
create_supply_port vdd -domain PD_Top -direction in
connect_supply_net vss -ports {leaf_wrapper/u_apb_ip/vss leaf_wrapper/u_ahb_ip/vss leaf_wrapper/u_axi_ip/vss}
connect_supply_net vdd -ports {leaf_wrapper/u_apb_ip/vdd leaf_wrapper/u_ahb_ip/vdd leaf_wrapper/u_axi_ip/vdd}

 Output TOP Level SDC 

set sdc_version 2.0
set_units -time ns
create_clock  -name  apb_clk_TOP -period  20.0 -waveform {0.0 10.0 } [get_ports u_apb_ip/pclk]
create_clock  -name  ahb_clk_TOP -period  10.0 -waveform {0.0 5.0 } [get_ports u_ahb_ip/hclk]
create_clock  -name  axi_clk_TOP -period  10.0 -waveform {0.0 5.0 } [get_ports u_axi_ip/aclk]
set_input_delay  2.0 -clock  apb_clk_TOP -max  [get_ports top_signal_b]
set_input_delay  2.0 -clock  ahb_clk_TOP -max  [get_ports top_trigger top_enable]
set_input_delay  2.0 -clock  axi_clk_TOP -max  [get_ports top_sync_i flag_out]

Benefits

  • Power awareness from day one: IP-level power domains flow seamlessly into SoC-level UPF.
  • Timing correctness ensured: Constraints are preserved and conflicts avoided during integration.
  • Automation reduces manual errors: Designers no longer need to hand-edit or re-create constraints at the top level.

Scalable for complex SoCs: Works smoothly with third-party, legacy, or in-house IPs.

Conclusion

By supporting UPF and SDC as first-class inputs, IDS-Integrate makes IP integration power- and timing-aware by construction. The tool automatically generates top-level collaterals that preserve intent, eliminate conflicts, and accelerate SoC assembly. As a result, designs are not only functionally connected but also optimized for power and timing closure—simplifying the path to silicon for today’s complex SoCs.

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