VHDL support now available in IDS-Verify

(Pinku Kumar)

Introduction

The first step towards verification is to understand the design specifications and accordingly build a test plan corresponding to it, then build a test bench and tests. After running the tests focus on the coverage. This is a long process requiring several hours if not days..

UVM provides some standard sequences, however, due to the fact that they are totally generic, you can only get ~40% coverage).

IDS-Verify comes in to bridge all these gaps where users just need to create their register specification and the entire UVM based verification infra (including formal assertions)  is generated on a click with close to ~100% out-of-the box coverage.

IDS-Verify has the following components :

  1. ARV-Sim: The Automatic Register Verification (ARV) simulation environment is generated.. It automatically generates the entire testbench and Makefiles for complete register verification.
  2. ARV-Formal: Formal verification can be done by extracting a list of properties from specification, each property describing a behavior of the design. These properties are used in formal tools to verify whether they are compliant with the RTL or not.
IDS-Verify

VHDL Support in IDS-Verify

IDS-Verify now supports VHDL RTL as DUT in a UVM-based verification environment. Users can provide their RTL in VHDL format and verify it using the generated UVM testbench. By specifying the output as “vhdl uvm arv” in IDSBatch, IDS-Verify automatically generates a verification environment with VHDL DUT support. This capability works from any supported input format—such as RDL, IP-XACT, XML, Word, or Excel—enabling broader adoption across both mixed-language and VHDL-centric design flows.

Use Cases

IDS-NG :

SystemRDL :

 addrmap block1 {
  reg reg1 {
    field{}f1[31:0]=0x4;
  };
  reg reg2 {
    field{}f1[31:0]=0x8;
  };
  reg1 reg1;
  reg2 reg2;
};

Output directory structure

 Output directory contains below files :

  1. RTL for Registers(VHDL/Verilog) : Hardware description code implementing the register logic in synthesizable RTL form.
  2. UVM Register Model : SystemVerilog UVM representation of the registers used for verification and testbench stimulus.
  3. Bus agents for APB, AHB,AXI,Proprietary etc. : UVM agents that provide protocol-specific drivers, monitors, and sequencers to interact with the DUT.
  4. SV Interface : SystemVerilog interface bundling signals and providing a clean connection between RTL modules and testbench components.
  5. Top-level module that instantiates the RTL and Interfaces : Module that instantiates the DUT (RTL) and connects it to interfaces, enabling integration with the verification environment.
  6. Sequences library : Collection of reusable UVM sequences to test registers.
  7. Makefiles : Build and automation scripts for compiling and running simulations.

Simulation result

Conclusion

With the addition of VHDL support, IDS-Verify takes another step toward making verification faster, more automated, and language-agnostic. Whether your design flow is based on SystemVerilog, VHDL, or a mix of both, IDS-Verify ensures that you get a complete UVM testbench, near-100% coverage, and seamless integration with formal verification—all directly from your specification. This enhancement empowers teams to accelerate verification closure and confidently adopt IDS-Verify across diverse design environments.

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