lp header

Webinar: Introduction to System RDL Part Two

SystemRDL 2.0 Register Description Language is the industry standard from Accellera used for describing control/status registers and memories in circuit designs.

We hope you enjoy the webinar.

HubSpot Video


eBook: How Agnisys Eliminates Redundancies in Semiconductor Design, Verification, and Validation

Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.


Recent Blog Articles

June 28, 2022

Tool Qualification Kit for Functional Safety Compliance

Introduction With growing advancements in hardware designs, the complexity of designs has increased multiple folds and brought great challenges to the lifecycle of quality management, development, validation, ...

June 28, 2022

Tight Generator Interface support in SoC-E

Introduction As per IP-XACT User Guide, IP-XACT defines an API called Tight Generator Interface (TGI) to query, modify, create, and delete IP-XACT XML documents. The standard defines this API in terms of SOAP (Simple ...

June 28, 2022

Chip-in-Chip support for multiple input format

Introduction  IDesignSpecTM supports multiple design hierarchies like “chip”, and “block” to enable different architectural design flows.  A block can contain registers. A chip can contain other blocks and provide an ...