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IDS-VerifyTM
Test and Testbench Specification Automation

IDS-Verify is a specification-driven verification solution that enables automated CSR (Control and Status Register) and hardware–software interface (HSI) verification for modern IP and SoC designs. It converts register specifications directly into a complete, simulation-ready verification environment, including UVM testbenches, verification sequences, coverage models, and assertions, enabling teams to achieve CSR verification sign-off efficiently and consistently.

Verification teams often spend weeks or even months building testbenches, writing sequences, and iterating to meet strict 100% coverage goals for CSR and HSI verification. This process is highly repetitive and resource-intensive, often involving manual testbench development, custom scripts, and continuous effort to maintain alignment between specification, design, and verification. Integration challenges across IPs, tools, and teams, along with repeated verification effort for every design iteration, further increase engineering effort and delay sign-off, ultimately impacting time-to-market.

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Continuous Alignment Between the Specification and Tests and Testbench Code

If your verification and software teams manually write sequences in their respective formats, they waste time and resources. There is a high likelihood of differing interpretations and the challenge of keeping the two teams in sync every time the specification changes.

Fortunately, Agnisys has IDS-Verify, a specification solution for automatic register test, custom register-based sequences, and testbenches in simulation as well as formal verification of registers.
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How IDS-Verify Enhances Your Development Process

IDS-Verify enables you to describe the custom configuration, programming, and test sequences of your design and automatically generate sequences ready to use during your RTL simulation. From a single sequence specification, IDS-Verify generates UVM sequences for verification and associated documentation. You specify the sequences using a rich language and command feature set that includes loops, branch, wait, calls, switch, and macros.
SEQUENCE VIEW
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Syntax and semantics checker and debugger

IDS-Verify includes a sophisticated syntax and semantics checker for the sequence descriptions to catch common user errors. The entire sequence specification is validated and a report containing a complete list of all problems opens in a window for viewing with cross-navigation to the specification row containing the problem.

Automatic generation of testbenches for verification

The generated UVM models and UVM sequences can easily be incorporated into your existing SoC or IP UVM-based testbenches. However, IDS-Verify also supports the ability to automatically generate a complete testbench-based verification environment and tests for automatically verifying all your addressable registers and memories with all access types and all complex types for IP and SoC designs.

The generated testbench is fully compliant with UVM, including bus agents, monitors, drivers, adaptors, predictors, and sequences, as well as Makefiles for common simulators. The UVM testbench is connected to the UVM register model and RTL design generated by IDesignSpec GDI, providing pushbutton verification.

Automatic generation of sequences

IDS-Verify automatically generates different sequences for the many types of registers supported by IDesignSpec GDI. including sequences for register fields, register-level sequences, and positive/negative sequences for special register types.

The generated UVM testbench can include sequences, configuration, checkers, coverage, assertions, and inter-component “plumbing” for your design in addition to memories and registers.

Automatic generation of assertions

IDS-Verify automatically generates SystemVerilog Assertions (SVA) for use in both simulation and formal verification.

Download the IDesignSpec Suite Brochure

View a summary of each product and how the suite enables your semiconductor teams to more rapidly develop products while improving efficiency.

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Benefits of IDS-Verify

The automatic generation of all these files for the project teams saves time and resources early in the project. Every file generated by IDS-Batch CLI is one that you do not have to code by hand. The correct-by-construction nature of specification generation also eliminates entire categories of bugs, accelerating verification and pre-silicon validation.

IDS-Batch CLI provides even more value every time that a specification changes. You simply run it to re-generate all relevant files. The key benefits are:

  • Eliminates manual update effort and ensures that all your teams are always in sync
  • Easy integration into your makefiles or check-in scripts for revision control systems
  • Easy integration into your continuous integration/continuous development (CI/CD) flows
  • Whenever a specification changes, IDS-Batch CLI can be run automatically on the command line and generate the updated files
  • All other Agnisys products also generate their outputs in command-line mode using IDS-Batch CLI

What Our Clients Say

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