Spotlight- 2016 Aug | Agnisys
In this world of uncertainty, engineers want guarantees in all aspects of System Development. To a large extend the sysdev process has been automated. However, problem areas remain, such as the actual design and verification process is not fully automated. Incidentally these areas are fraught with a lot of uncertainty leading to delays in schedule and cost overruns.
How can the certainty and confidence in System Development be improved, and uncertainty eliminated altogether?
In this issue we bring you examples and case studies about how system development teams – hardware design/verification and software/firmware teams can reduce and eliminate the uncertainty from their system development process.
The Agnisys Team is pleased to bring to you this new quarterly newsletter that will shine the Spotlight on the latest from the System Development trenches. We will share with you how customers are using Agnisys tools capitalizing on the latest features. Your comments and participation is welcome.
– Anupam Bakshi, CEO, Agnisys, Inc.
How do you create Indirect Registers interface to a slower but wider EEPROM?
In digital design, especially those with area and power constraints, the data and address buses have smaller bus width. One of the direct impacts of the limited address bus width is the limited address space that can be accessed by the design.When you have a limited address space, but you have a need to access a larger memory, you have only a few options to choose from. You can either address a larger space indirectly, or you can play some games with address paging. Here we will talk about the first option – using indirect address map and how to implement them in IDesignSpec™. Using IDesignSpec, we can create indirect access of a memory thru two registers. Learn how
How to setup streaming communication between the host and the application logic?
Invariably modern systems have hardware and software components. The communication between hardware and software is done using a variety of constructs such as registers, memories, interrupts, FIFOs etc. These constructs enable both the domains to send system information to each otherIDesignSpec (IDS) is a tool to create the memory mapped registers and memories. It can also be used to create interrupt trees and FIFOs. It enables you to create a variety of FIFOs with configurable clock handling, its size and location in memory space, how to deal with thresholds, full/empty flags etc. Learn how
