Spotlight – 2017 Feb | Agnisys

Thanks for reading the first issue of the Newsletter for year 2017. As usual, this newsletter comes directly from the Engineering team that is constantly working on improving the products based on our interactions with our customers and industry standards. We focus on Designs in IP-XACT, the value add of Automatic Register Verification using simulation and formal. We believe that we can completely eliminate manual verification for areas of the design where the specification is formally specified – like the case of register and memory map.

While I have your attention, I will like to point you to a new blog that is based on my recent experiences
Circle of Work Life.

– Anupam Bakshi, CEO, Agnisys, Inc.

IP-XACT is an industry standard IEEE 1685-2009/2014 which is recognized by the electronics community as the most appropriate choice for properly and efficiently managing Electronic System Level (ESL) flows. With more complex System Level Designs and IP Components, it is difficult for design and verification engineers to build, integrate, update and verify the design hierarchy. The IEEE 1685 IP-XACT standard was designed to fit this requirement. It not only supports the creation of IP and Design level documents but also provides a mechanism for their interconnection.

What is IPXACT?

IP-XACT describes an Extensible Markup Language (XML) data format and structure, governed by a schema for capturing the meta-data, which captures the design of intellectual property (IP) used in the development, implementation, and verification of electronic systems.
IP-XACT schema defines a number of document types, and a set of semantic rules that describe the relationships between those documents. Read more

Accuracy of Register Verification

Register verification is a significant part of the design verification problem. It is one of the first aspects of the design that must be tested because the rest of the semiconductor functionality depends on the accuracy of the register implementation. That is because registers contain the configuration setting of the hardware and is the basis of the hardware / software interface.
A Verification Engineer has to develop a coverage driven models manually to verify a design. So s/he has to spend a large amount of time in verifying the functionality of a register and memory map of the design. This issue is futher exasserbated when there are a large number of IP with registers in an SoC design. Read more

Formal verification using ARV-FORMAL

Formal verification avoids the slowness of event-simulation by using mathematical algorithms and heuristics to prove the functional correctness of a design. Popular specification standards such as IP-XACT , SystemRDL, CSV’s have been used as a starting point for automatically generating any Register Models, RTL, Firmware , and Verification Code . The whole verification process can be further upgraded by automating code for formally verifying IP’s with slave interface , since it helps in reducing simulation efforts and the overhead involved in creating and maintaining block/chip level test-benches. By using directed and constrained random test-cases we may miss out corner cases, which can only be verified formally. Read more

Indirect Registers inside Reggroups

In memory mapped digital designs, when you have a limited address space, but you have a need to access a larger memory you use indirect address space. Indirect address space is typically implemented using an index register, a data register and an indirectly addressed memory. IDesignSpec fully supports this scheme in both RTL and UVM.

Recently, we came across a situation where our customers were using the indirect registers inside the reggroups, in addition, the bus width for the direct and the indirect bus was different. This required some specially handling in UVM and RTL. We supported indirect register inside the reggroups with different bus widths .Read more