Newsletter 2023 Q3
Agnisys offered a remarkable number of improvements for the IDesignSpec suite in the third quarter of 2023. We are moving forward with our goal of offering a golden specification-driven, all-inclusive development flow.
Beginning with this newsletter, we will include a section titled “Steps to Start Using” that will include detailed instructions for you to use the feature as soon as it is installed. We sincerely hope you find the new features useful and immediately put them to use.
Here are some of our most significant IDS improvements:
- Search by address in HTML
- Glue logic in IDS-Integrate
- Datasheet name format
- Byte access errors for external registers
IDS provides support for an HTML feature that lets users easily search for components by using their addresses. This functionality makes it easier for users to quickly access particular HTML output components, which greatly enhances user experience. Users can now search for other components, such as Chip, Block, Section, and Register, thanks to the increased capability. Read More
The term “glue logic” describes the digital circuit or components that are utilized to connect ports from various blocks or IP addresses. Basic digital logic gates and operations (AND, OR, XOR, and NOT) & MUX or other combinational/sequential digital logic can be used as the glue logic. It is possible to utilize multiplexers as glue logic in the IDS-Integrate connection API. The purpose of glue logic connection is to enable MUX port-to-port connections between blocks and IP addresses. By improving the soc_connect API, connections with glue logic activities may be formed with just one command. Read More
Only the names and access details of the registers, as well as the bus information, are contained in the datasheet. When there are identical register names, duplication occurs when there are no explicit details for any other hierarchy. With the aid of the “*_name_format” attribute, there is a feature in the RTL, RAL, and header outputs that allows the removal of duplicate register names when two identical registers appear under distinct blocks. This function is now supported in the datasheet output as well. Read More
The capability to write individual bytes of data within a large information word is known as byte access. Which bytes on a data channel are enabled for writing during a transfer operation is determined by logic. A property called “external_byte_acc_err” in IDesignSpec is supported. While any of the “byte_enable” control lines are equal to zero, this property gives an error signal to be generated while accessing the external register. Read More
