Agnisys is excited to exhibit at DAC 2025, showcasing our latest innovations in design automation, embedded systems, and standards-driven development. Stop by Booth #2622 on the 2nd floor to discover how we’re enabling faster, smarter, and more interoperable hardware design through automation and collaboration.

Agnisys has announced version 9 of IDesignSpec Suite

• Simplified use model, imported user interface
• Support for latest standards: CDC, UPF, SDC, IP-XACT
• Verify, Validate updates, support for VHDL
• Java & C/C++ API for custom plugins 
• Bus interfaces, Bridges, convertors, crossbars, decoders for addressable buses used in SoC design 

IDS-Integrate Enhancements

• UPF, CDC and SDC support (Reading and Generation Level)
• Generation of C/C++ header, Documentation 
• Git Integration
• Plugin using Java or C++ API
• API Hinting support in Visual Studio Code
• IP-XACT 2022 Support
• Full SV support (Reading and Generation)

IDS-FPGA

Agnisys’ most popular product for front-end automation – The IDesignSpec Suite, has been repackaged & repurposed for FPGA users. It’s called IDS-FPGA.
Users can create the register map & programming sequences for their FPGA design within their FPGA tools and generate Design, Verification, Validation collateral with a click.
Design files can be Verilog, SV or VHDL, UVM model, testbench, tests & programming sequences are generated in Verification.
C/C++ based programming sequence that runs in the FPGA Validation env to the FPGA prototype board.
Currently AMD Vivado & Altera Quartus are supported. 

AI**2 : Agnisys Inc. Artificial Intelligence

The predicted end of manual verification is here using AI. With the new AI**2 collaboration platform, Agnisys has announced significant reduction in testbench and test creation time. More details.

Engineering Special Session

Join Agnisys and Accellera experts as we explore the importance of standardized and interoperable collateral for Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis. Discover how standard abstract models enable hierarchical CDC/RDC closure, enhancing tool interoperability, design accuracy, and overall verification efficiency.

Title: CDC-RDC Inter-operable Collateral Standardization
Date: Monday, June 23, 2025
Time: 10:30 AM – 12:00 PM PDT

So drop by our booth and collect a rare gift and also participate in a raffle to win an electronic kit.