Introduction
Agnisys has developed a Programmer's Reference Manual (PRM) that serves as a comprehensive documentation resource for “programming sequences” and hardware addressable register architecture. It is intended to be a key reference for programmers, developers, and individuals seeking a detailed understanding of the intricacies of the design being developed.
Agnisys' PRM comprises three views that are beneficial for users:
Register View: This view provides complete information on addressable register and memory data.
Sequences Tabular View: This section presents detailed information about sequences in a tabular format. Users can conveniently track and access information related to each sequence.
Flowchart View: This view includes a graphical representation or flowchart illustrating the sequences, offering a visual understanding of the information flow.
Steps for Generating PRM Using IDS-Validate
A sequence is a “set of steps” that involve writing/reading specific bit fields of the registers in the IP/SoC. This sequence can be simple or complex, involving conditional expressions, an array of registers, loops, etc. Users can write a single sequence specification from which an Agnisys compiler automatically generates UVM sequences for verification, SystemVerilog sequences for validation, C code for firmware and device driver development, and various output formats for Automatic Test Equipment (ATE).
Use Case
IDS-Batch CLI:
Users can generate PRM output using the following command:
Command Line
idsbatch <input_file> -out “iss_prm” -dir <user_defined>
IDesignSpec GDI:
Users can generate the PRM by adding the following command in the configure window:
Figure 1- Configuration Setting
Example
Input Sequence Specification:
Figure 2- Input Sequence Specification
PRM Generated Output:
Register view:
Figure 3- Register view
Tabular view:
Figure 4-Tabular View
Sequence view:
Figure 5- Sequence View
Conclusion
IDS-Validate is a useful tool that simplifies the verification of complex systems by creating and managing models of hardware registers. By automating test generation and facilitating reuse, IDS-Validate saves time and effort in system verification. The ability to generate C code equivalents of sequences adds flexibility to the testing process. Overall, IDS-Validate enhances reusability and scalability, making it an effective solution for the verification of sophisticated system-level designs. From the golden custom sequence specification in a single file, IDS-Validate can generate PRM outputs such as :
- Register information in HTML format
- Tabular information about custom sequences
- Flowchart of the custom sequences
