Putting All the Pieces Together with IDS-Integrate

There are countless challenges at every stage of system-on-chip (SoC) design. Just defining the overall architecture involves many iterations through virtual platforms and high-level models. You must make key decisions about processors, buses, interfaces, and more. For every function, options for internal and external IP sources must be investigated. For any parts of the design where existing IP is unavailable or inappropriate, your designers must write and verify the register transfer level (RTL) code. Finally, your integration team must pull all the pieces together into a top-level design to be verified and validated using system software.

SoC Integration Challenges

It might seem that assembling the IP blocks into a full chip isn’t so hard. All the pieces are well defined, either through access to source RTL or a description format such as IP-XACT. In actual practice, this is a tedious and error-prone process. You must interconnect hundreds of thousands of IP inputs and outputs, perhaps even millions. You may have dozens of levels of hierarchy under the top level, so integration happens at many places in your design.

Replicated IP blocks and similar signal names make manual interconnection risky, subject to typos and simple misunderstanding of what connects to what. Signal names change frequently as they traverse up and down your design hierarchy, adding to the confusion. Connecting blocks together often involves more than just IP-to-IP wires. Multiple buses require “widgets” such as bridges, converters, aggregators, multiplexers, and crossbar interconnects to join them together.

On top of all these challenges, integration is not a one-time task. Your design evolves frequently over the course of your project, and many changes will affect your hierarchy and connectivity. Every such change means that you have to modify your interconnections, often at multiple design levels, with a renewed risk of errors. This consumes designer resources to make the changes as well as verification resources to ensure that no new errors were introduced.

Automated Integration to the Rescue

To address all these challenges, several years ago we introduced IDS-Integrate™, one of the components of our IDesignSpec™ (IDS) Suite of products. IDS-Integrate provides a flexible and customizable environment for hierarchical assembly of both your own designs and commercial IP blocks into an SoC. It supports the IP-XACT standard used by many IP providers, so proprietary RTL code is not required. Using IP-XACT, you can also connect your own blocks before the RTL design is ready.

To deal with replicated and similarly named blocks and signals, IDS-Integrate defines a simple but powerful specification format for you to describe your block interconnection. Each wildcard can eliminate the need to connect hundreds or thousands of signals manually. You can connect blocks at every level of your design hierarchy, up to the top level of your SoC. You can generate and view schematics to see the results, and run design rule checks to ensure IP and SoC quality.

IDS-Integrate automatically generates all widgets needed to connect your buses safely together. For example, if your design includes a processor using the AXI4 high-speed system bus and a lower-speed peripheral block using the APB bus, we generate an RTL AXI4-to-APB bridge and add it to your SoC design. Finally, our Smart Assembler technology can create templates for new blocks based on existing blocks and “promote” signals in the hierarchy to become top-level SoC pins.

IDS-Integrate Grows Even More Powerful

At Agnisys, we never stand still. We’re constantly keeping an eye on new technologies we can adopt, including increasing use of AI, and working closely with our users to identify new problems we can solve. IDS-Integrate is no exception. We have added several new capabilities as the direct result of our careful attention to industry trends. This has resulted in a more comprehensive solution attuned to the needs of today’s SoC developers.

With the introduction of our Silicon IP Portfolio, IDS-Integrate has a much greater variety of bus widgets for you to select from. Recent additions include crossbar interconnects, bus decoders, and bus converters that connect buses with different data widths. This gives you more flexibility to include multiple buses in your SoC while letting us handle the interconnection completely.

IDS-Integrate now interacts with the Library Exchange Format (LEF) and Design Exchange Format (DEF) files generated by place-and-route (P&R) tools. These files represent the complete physical layout of the SoC. If you provide these files, IDS-Integrate will check them against the design and make any necessary changes in the assembled hierarchy for consistency.

IDS-Integrate Grows Even Smarter

IDS-Integrate is now power-aware, supporting the Unified Power Format (UPF) standard. This format defines the power intent of an IP, including power domains, supply nets, and connectivity. By reading UPF files during integration, IDS-Integrate ensures that hierarchical power structures are preserved while structuring the design hierarchy and are seamlessly rolled up into a SoC-level UPF description.

Similarly, IDS-Integrate is constraint-aware, supporting synthesisdesign constraint (SDC) files. These capture IP-specific timing constraints such as clock definitions, input/output delays, and setup/hold requirements. Integrating these constraints prevents conflicts between multiple IP blocks and ensures SoC-level timing closure. IP-level SDC files are consolidated into a coherent SoC-level constraint set.

When you provide both UPF and SDC, IDS-Integrate automatically generates top-level collaterals (UPF+SDC) that are hierarchy-aware and consistent across all IPs, thereby reducing manual intervention. The generated full-SoC RTL, UPF, and SDC descriptions are consistent and ready for downstream design implementation and verification.

We allow you to extend the functionality of IDS-Integrate even more through customization via an application programming interface (API). We support API access from Java, C++, or Tight Generator Interface (TGI), a part of the IP-XCT standard.

Summary

This post covers some of the key capabilities we provide to make your chip integration and assembly easier, faster, and correct by construction. There are a lot of other, less visible improvements in the most recent versions of IDS-Integrate. For we have increased our awareness of Git, commonly used for version control. We’re always looking for ways to improve performance and make your life easier. As we said, we’re never standing still, so you can expect more exciting features all the time.