August 11, 2019

Repurposing von Neumann Architecture with SRAM-based Register Files

By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades, but with the advent of AI applications and big data the entire industry has put a spotlight on its limitations. Since massive amounts of data need to travel back and forth between the CPU and memory, the resulting latency and power consumption became major issues. One of the powerful ...

May 20, 2019

Not your Average UVM Testbench Generator – Unveiling at DAC 2019

By Louie De Luna, Agnisys Chief Product Evangelist Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t really appreciate the impact of the ...

April 15, 2019

EDA Is Advancing – but Where Are the Women?

By Ishanee Bajpai – Senior Marketing Executive, Agnisys 1981 marked the beginning of EDA as an industry. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.  As the ...

March 26, 2019

Setting the Stage for the Next Abstraction

By Louie De Luna, Agnisys Chief Product Evangelist As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to schematics to ...

December 17, 2018

Top 2018 Agnisys Resources

Every year we take a look back at the resources we’ve created to determine what you’ve found most useful. We invite you to take a look below at our top viewed and downloaded resources from 2018. RECORDED ...

December 3, 2018

Automating Register Verification with 100% Functional Coverage

 By Louie de Luna, Agnisys Director of Sales and Marketing UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics ...

October 30, 2018

What ARE the Root Causes of Functional Flaws?

By Louie de Luna, Agnisys Director of North American Sales and Marketing Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. ...

August 24, 2018

Out of the Office – Lessons from a client visit in Edinburgh

As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a bit of tunnel vision as we busy ourselves with client meetings, conferences, socializing with potential new clients, ...

April 11, 2016

The Ultimate Shift Left

Important observations from Einstein and New England’s ice traders.. Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several ...

December 30, 2015

2015 Year End review – DV Challenges

Wow what a marvelous year 2015 has been to Agnisys, with full of events at the various technical exhibitions, new customers, new features and new products and not to forget – new partnership. It would be unfair to say ...

September 21, 2015

Does UVM sometimes make you feel stupid?

Somewhere in the deep trenches of a UVM based verification project, an engineer teeters on the verge of insanity. As the saying goes, the faint of heart need not attempt UVM based verification. But what makes it so ...

July 22, 2015

Questa® VIP validates IDesignSpec generated IP

In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If we take a look at the AMBA®AXI4Lite bus protocol, it has different channels for ...

July 11, 2015

Semiconductor Data Sheet Automation – Just The Way You Want It

Moore’s law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of technology. But, along with this, a new complexity takes shape in the form of documentation for ...

June 27, 2015

Electronic Design Automation Trade Show Update – 52DAC

Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher levels of productivity. I find that interesting as we at Agnisys have been doing this left shift since ...

May 28, 2015

How To Create Complex Registers in IDesignSpec

We talk about creation of complex registers in IDesignSpec, generation of their suitable RTL and UVM models. The Software addressable registers in your design do not always just have simple read-write access. Sometimes ...

March 4, 2015

Semiconductor Register Specification: Shadow of a Shadow

So we have been working in the register specification space for a long time. We came out with the IDesignSpec tool around 2010. Five years of constant refinement and evolution based on the customer feedback has created ...

December 10, 2014

CERN Selects IDesignSpec for The TOTEM Experiment Project at the Large Hadron Collider

The Large Hadron Collider (LHC) at CERN is the worlds largest and most powerful particle accelerator. This research facility enables some of the most advanced scientific experiments.  The TOTEM experiment is dedicated ...

October 30, 2014

DVCon Europe Needs Automatic Register Verification and Generation

I feel like a bumblebee, going from the DVCon in US, to the next one in India to then to Europe.  All this cross-pollination is exciting and enriching when experiencing the needs of the Semiconductor design engineers ...

September 26, 2014

DVCon India takes off!

DVCon had a solid start in Bangaluru, India.  The audited attendee numbers will be coming in later, but we believe we had approximately 425+ delegates. That is truly amazing for the first year of the event! For me, it ...

September 24, 2014

Getting Ready for DVCon India 2014

It is penultimate day – the day before the big event! Preparing and launching the first ever DVCon India event feels like taxiing a plane down the runway, ready to take off.  It is new; the design was replicated from ...

July 17, 2014

What Every Engineer Should Know About SoC Register Generation

Register Generation is a Must-Have Capability Today’s SoC designs contain several thousands of registers and memory map elements. The design team must, from the architecture, create the register and memory map ...

July 17, 2014

The 5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

Modern SoCs get more and more complicated each and every day.  As the complexity of modern electronic semiconductor device design increases, niche tools for every nook and cranny of the design process emerge to help ...

System On Chip Design Challenges Addressed by Agnisys
June 4, 2014

DAC Day 2: System On Chip Design Challenges Addressed by Agnisys

System on Chip Design Challenges – The Highlight of DAC Day 2 It was a very busy day for Agnisys on the second day of the Design Automation Conference. On day two, we learned how much our products address System on Chip ...

September 10, 2013

EDA Companies must Collaborate or Die

  Recently at the sidelines of DAC, Anupam Bakshi, CEO of Agnisys, Inc. sat down with Karen Bartleson, Director of Community Marketing at Synopsys to discuss a very important topic that is close to the heart of the ...

May 28, 2013

Using IVerifySpec to test IDesignSpec: A case of doctor eating his own medicine!

IDesignSpec generates several outputs from a single spec. We started out as a simple tool that just dealt with registers. After 6 years the tool has metamorphosed into an Executable Spec tool for Digital design. This ...

May 28, 2013

IDesignSpec Provides Complete Register Design Automation

Published on 05-19-2013 07:30 PM in Semiwiki It goes without saying that registers play a vital role in designing any ASIC, FPGA, SoC or System. In today’s world, while designing SoC with multiple IPs and ...

May 28, 2013

Agnisys makes Design Verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs ...

December 7, 2012

Begin Initialization Sequence – 10, 9, 8, …

Launching new capability to specify Sequences in IDesignSpec

July 28, 2009

Great turnout at the Design Automation Conference

We had a great first day at DAC. All the talk about recession and economic doom were hard to believe. People were enthusiastic and upbeat. Even the guys and gals looking for work were upbeat and were considering it to ...

June 17, 2009

First sale is always sweet!

I’m thrilled. Finally, we have a customer who sees the value that IDesignSpec brings for his company. We are indeed thankful to them for trusting our technology. I think this is validation of the concepts on which this ...

May 25, 2009

Is cheap EDA tool an oxymoron?

Business schools teach us that the way to set the price on a product has nothing to do with the cost. You sell it at a price that the market can afford. Semiconductor industry was able to afford heavy price tags on EDA ...

April 25, 2009

Why is it difficult to make your first EDA tool sale?

As you know we have created a brand new EDA tool that saves people a lot of time and money. Ok you have heard that before. But this is real 🙂 Ok so you have heard *that* before too! So how do I convince you to take a ...

April 24, 2009

IDesignSpec: An Engineering tool with a difference.

I’m so excited … After years of work, my team and I have converted a word processor into an Engineering tool. Its like the Gene in Arabian Nights who says ” your wish is my command” … except in this case, your word is ...