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DVCon India takes off!

DVCon India takes off!

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DVCon had a solid start in Bangaluru, India.  The audited attendee numbers will be coming in later, but we believe we had approximately 425+ delegates. That is truly amazing for the first year of the event!

DVCon-India-LeadershipFor me, it was a long-standing desire, ever since I started going to DAC in US in 1994, to have conferences such as DVCon and DAC in India. Of course it was the entire steering committee and the Technical Program Committees and most of all, Accellera that made DVCon India possible.  So I will say a BIG “Thank You” to them all.

The first day of DVCon India started out with the lamp lighting ceremony, unique to India, which Wally Rhines graciously obliged. Wally’s talk was about trends in verification. One of trends he highlighted was how System Verilog and Universal Verification Methodology (UVM) is ruling the verification world. A second was how high level stimulus is important for verification productivity gains.

DVCon India PresentationMy UVM-SystemC presentation that was prepared by Martin @ NXP was very well received. I was surprised to see great anticipation in the SystemC community for this work. What was most interesting to the UVM-knowledgeable folks sitting in the audience was how closely the UVM-SystemC resembles UVM-SystemVerilog. But the real value add, besides just the change in the language was the fact that you could take the entire UVM-SystemC environment and target hardware such as an ARM processor, not to mention the speed up in the native simulation speed over SystemVerilog.

In the evening I was fortunate to attend the latest UVM-SystemC meeting and update the development team in Europe about the excitement and anticipation of this library. Agnisys will support this development work in every way possible.

Agnisys Booth DVCon IndiaOur booth got major attention by the crowd. Delegates were especially interested in the advanced capabilities of IDesignSpec – such as Automatic Register Verification (ARV) and quirky registers.

DVinsight – our smart editor cum linter for UVM code got very many likes. All visitors saw the value that DVinsight brings to the table – one is being lightweight – almost like vi/emacs and then the various UVM checks it automatically does. Speaking of UVM checks I also attended Duolos’s presentation on “Easier UVM” where they talked about the coding guidelines for UVM. I’m happy to say we cover a lot of these checks and suggestions in our tool.

The cocktail party in the evening was a fitting end to the hectic day. Now onto the 2nd and final day tomorrow. 

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