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Advanced UVM RAL

The verification of large or complex designs targeted at ASIC/FPGAs is time consuming. However, with a good testbench architecture the workload can be greatly reduced.The UVM register layer classes are used to create a high-level, object-oriented model for memory-mapped registers and memories in a design under verification (DUV).An IDesignSpec (IDS) register model is an instance of a register block, which may contain any number of registers, register files, memories, and other blocks. Each register file contains any number of registers and other register files. Each register contains any number of fields, which mirror the values of the corresponding elements in hardware. Likewise, IDS can generate Register Callbacks, Register Arrays, Memories, Indirect Access Registers, FIFO Registers, Alias Registers, Interrupt Registers, Lock Registers and Coverage Models that are supported by the UVM register model in its UVM output.

This webinar will discuss advanced constructs in UVM RAL and how IDS can be used to automatically generate them.

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Event Info:
Date :  April 30th, 2020
Time: 10:00 AM-11:00 AM PDT

Presenter: Nitin Chaudhary, Agnisys R&D Engineer

By April 30, 2020

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