In functional verification, sequences play a vital role in verifying that the logic design abides by the specification. These stimuli are further translated by the drivers into the actual inputs of the design under verification.
Overcoming the lack of a common set of sequences that can be shared across the teams, ISequenceSpec (ISS) enables users to describe the programming and test sequences of a device and automatically generate sequences, which can be used from an early design and verification stage to post silicon validation. ISS helps design, verification and validation teams to generate the unified test and programming sequences for various platforms, including SV, UVM, firmware, Tcl, etc. from a single specification.
Date : April 9th, 2020
Time: 10:00 AM-11:00 AM PDT
Presenter: Amanjyot Kaur, Agnisys R&D Engineer