In this webinar, we explored how Agnisys IDS-Integrate addresses the complexity of SoC design by automating IP block integration. The session demonstrated how predefined TCL and Python-based APIs can significantly reduce manual RTL coding, while features like automatic connectivity, hierarchy manipulation, and TGI (Tight Generator Interface) access help streamline design workflows. Attendees saw how IDS-Integrate enhances productivity, ensures design consistency, and accelerates front-end development for complex SoCs.
eBook: How Agnisys Eliminates Redundancies in Semiconductor Design, Verification, and Validation
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.
As the art of chip design began to mature, interconnecting major blocks required more than just ad hoc collections of signals...
Introduction As SoC designs continue to grow in complexity, the communication infrastructure connecting various IP blocks becomes increasingly important. Traditional...
Agnisys will showcase IDS-AI™, IDS-NoC™, and Advance DFT Automation at DAC 2026 to accelerate chip design, improve quality, and...
