Interview of Anupam Bakshi by Sanjay Gangal, EDA Cafe
Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.
Automatic generation of the RTL design will continue beyond the hardware-software interface (HSI) layer. It will encompass a whole custom IP, enabling users to generate much of their design directly from their specifications. The generation process will include high-quality documentation suitable for inclusion in user manuals.
Automatic verification will continue to include not only testbench generation but test generation as well, plus generation of assertions for use in both simulation and formal verification. Generated C/C++ code will be used by programmers to develop and test their embedded code and device drivers.
Finally, the RISC-V movement will continue moving along briskly with greater need of automated solutions for IP and system level modeling.
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.