Introduction
Sachin Pareek
In modern systems, especially those with complex designs and changing configurations, flexible memory management is very important. A key feature that supports this flexibility is the “remap state”. This allows the system to adjust memory address mappings based on different configurations or states. This is especially useful when the address space of a component changes due to design variations or runtime conditions.
In addition to remap states, remap ports play an important role in managing these changes. Remap ports allow for quick switching between memory addresses as needed. For example, consider a system with two counters—one that counts up and one that counts down. Remap states and ports can be used to switch between their memory addresses, enabling dynamic adjustments to the memory map as required. This approach makes memory management more efficient and adaptable to varying operational conditions.
The concept of remap states was introduced in IP-XACT and is a central concept for dynamic address mappings based on design variation and runtime conditions. Agnisys product supports this feature through a couple of properties as explained in this article.
How Remap States and Ports Works in IDesignSpec
In IDS, a remapState defines a specific configuration of memory address mappings. It is used to describe how memory addresses should be arranged under different conditions or configurations. The state attribute within the memoryRemap element refers to a specific remapState by name, indicating which memory mapping is active for that configuration. Each remapState element is associated with a unique name and a description that explains its purpose within the design. Multiple remapStates can be defined within a memoryMap element, allowing for different memory configurations to be applied based on the system’s requirements. A remapPort, on the other hand, is a hardware signal or port used to control the selection of a remapState. It allows the system to dynamically switch between different memory mappings during runtime. The remapPort element specifies whether the port is a single wire or a vector, which determines the number of bits involved. Additionally, the description attribute of the remapPort provides a detailed explanation of its behavior and interaction with the remapStates. Through the remapPort, the active remapState is selected, enabling the system to adapt its memory configuration based on the current operating mode or conditions. IDS can convert SystemRDL to IP-XACT format for hardware design. It also helps create IP-XACT files for header files and UVM to simplify verification.
SystemRDL Input:
property chip{type=boolean; component=addrmap;};
property remap_state{type=string; component=addrmap;};
property remap_port{type=string; component=addrmap;};
addrmap chip1{
chip=true;
addrmap Block1{
remap_state="abc";
remap_port="doRemap:0x0";
reg reg1{
regwidth=32;
field {
hw= rw;
sw= rw;
}F1[31:0]=32'h0;
};
reg1 reg1;
};Block1 Block1 @0x00;
addrmap Block2{
remap_state="xyz";
remap_port="doRemap:0x1";
reg reg2{
regwidth=32;
field {
hw= rw;
sw= rw;
}F2[31:0]=32'h0;
};
reg2 reg2;
};Block2 Block2 0x00;
};
IPXACT Input/Output:
Below is an IPXACT example of a remap_state and remap_port. This design, generated by IDesignSpec.
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:remapStates>
<spirit:remapState>
<spirit:name>abc</spirit:name>
<spirit:remapPorts>
<spirit:remapPort spirit:portNameRef="doRemap" spirit:portIndex="1">0x0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
<spirit:name>xyz</spirit:name>
<spirit:remapPorts>
<spirit:remapPort spirit:portNameRef="doRemap" spirit:portIndex="1">0x1</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
</spirit:remapStates>
<spirit:memoryMaps>
……………………………………………………………………
…………………………………………………………………..
……………………………………………………………………
…………………………………………………………………..
<spirit:memoryRemap spirit:state="abc">
<spirit:name>DEF</spirit:name>
<spirit:addressBlock>
<spirit:name>block1</spirit:name>
<spirit:description/>
…………………………………………………………………………..
…………………………………………………………………………..
…………………………………………………………………………..
</spirit:addressBlock>
</spirit:memoryRemap>
<spirit:memoryRemap spirit:state="xyz">
<spirit:name>xyz</spirit:name>
<spirit:addressBlock>
<spirit:name>block2</spirit:name>
<spirit:description/>
………………………………………………………………………………………
………………………………………………………………………………………
Header output:
Below is a cheader example of a remap_state and remap_port. This design, generated by IDesignSpec.
#include "Block1.h"
#include "Block2.h"
/*////////////////// Chip : Chip1 ///////////////////*/
#ifndef _CHIP1_REGS_H_
#define _CHIP1_REGS_H_
/* chip : Chip1 */
typedef struct {
union {
Chip1_Block1_s s;
hwint8 filler[0x4];
} Block1;
union {
Chip1_Block2_s s;
hwint8 filler[0x4];
} Block2;
} Chip1_s;
#define Chip1_s_SIZE 0x4
#define Chip1_s_OFFSET 0x0
#define Chip1_s_ADDRESS 0x0
#endif
UVM Output:
Below is an UVM example of a remap_state and remap_port. This design, generated by IDesignSpec.
class chipmodel_block extends uvm_reg_block;
`uvm_object_utils(chipmodel_block)
rand chipmodel_chipblock1 chipblock1;
rand chipmodel_chipblock2 chipblock2;
uvm_reg_map abc;
uvm_reg_map xyz;
virtual function void build();
//define default map and add reg/regfiles
abc = create_map("abc", 'h0, 4, UVM_BIG_ENDIAN, 1);
xyz = create_map("xyz", 'h0, 4, UVM_BIG_ENDIAN, 1);
default_map = xyz;
chipblock1 = chipmodel_chipblock1::type_id::create("chipblock1");
chipblock1.configure(this, null, "chipblock1");
chipblock1.build();
chipblock1.map(abc, 'h0);
chipblock2 = chipmodel_chipblock2::type_id::create("chipblock2");
chipblock2.configure(this, null, "chipblock2");
chipblock2.build();
chipblock2.map(xyz, 'h0);
lock_model();
endfunction
virtual function void map(uvm_reg_map abc, uvm_reg_map xyz, uvm_reg_addr_t offset);
chipblock1.map( abc, offset + 'h0);
chipblock2.map( xyz, offset + 'h0);
endfunction
virtual function void set_offset(uvm_reg_map abc, uvm_reg_map xyz, uvm_reg_addr_t offset);
chipblock1.set_offset( abc, offset + 'h0);
chipblock2.set_offset( xyz, offset + 'h0);
endfunction
endclass
Conclusion
In modern digital design, the ability to dynamically adjust memory mappings is critical for creating systems that are both flexible and efficient. IDS offers a robust mechanism for managing these changes through remap states and remap ports. By utilizing these components, designers can ensure that their systems are adaptable to varying configurations, improving performance, scalability, and overall system reliability. Understanding how remap states and ports work in IDS is essential for building advanced designs that can respond to the ever-evolving demands of modern applications.
