Newsletter Q4 2016 Detailed Content

Simplify IP-XACT flow for IP/SoC development

IP-XACT from the IEEE 1685-2009/2014 is nowadays recognized by the electronics community as the most appropriate choice for properly and efficiently managing Electronic System Level (ESL) flows. IP-XACT describes an EXtensible Markup Language (XML) data format and structure, documented with schema for capturing the meta-data, which documents design intellectual property (IP) used in the development, implementation, and verification of electronic systems.

The primary goals of the standard are:

  • To enable IP vendors to provide a single description of their components to all of their customers, regardless of the design language or tools that they use
  • To enable developers to transfer designs between environments that use different design languages.

IP-XACT includes an XML schema that defines a number of document types, and a set of semantic rules that describe the relationships between those documents. The most important types of documents are:

  • Design documents
  • Component documents
  • Bus definition documents.
  • Abstraction Definition documents

IDesignSpec generate all above mentioned IP-XACT documents corresponding to a Register Specification.

An IP-XACT component is the central placeholder for the object‘s meta-data. Components are used to describe cores, peripherals, and buses. IDesignSpec can easily import and export IP-XACT in all flavors – be it Word, Excel, OpenOffice, SystemRDL or CSV. User can generate various outputs using IP-XACT in IDesignSpec and SOC Enterprise.

ip1The top-level described in register spec using IDS and SOCE is converted to spirit:component, which includes additional properties like vendor, library name and version.

ip2

<spirit:memoryMaps>is an unbounded list of memoryMap elements, which is contained inside <spirit:component>. The chip in IDS is converted to <spirit:memoryMap> element inside <spirit:component>.

Following is the list of IDS component which maps to IP-XACT element.

ip3Import of IP-XACT is also very easy in order to make a spec document.

ip4ip5

SOC Enterprise collects the metadata and converts it to the desired IP-XACT format. User can generate and also import IP-XACT to create its design in SOCE. In SOCE user can provide its information related to a design in following sheets – Sheets

  • General
  • Parameters
  • I/O Ports
  • Interfaces
  • Electrical
  • Physical
  • Enumeration
  • Views
  • IDS Template

ip7

Electrical information described in SOCE goes in vendor extensions of IP-XACT output:

ip8

User can also edit the IP-XACT inside the SOCE and can generate its design component.

ip9

The above IP-XACT can also be converted to graphical view and to other outputs:

ip10

SOCE can be used for IP-XACT packaging of a Design specification.

In summary, we have shown how simple and straightforward it is to create an IP-XACT description of a Register spec and Design using IDesignSpec. For further information and updates, please refer to the online documentation or send an email to our support team.

 For further information and updates, please refer to the online documentation or send an email to our support team support@agnisys.com.

Automatic Datasheet Generation with IDesignSpec

One of the real advantages of IDesignSpec is its ability to create Word output files from register specifications. This allows you to automatically document the register specification for everyone on your project. The format of the output files can be specified via user defined templates. IDesignSpec understands special keywords that are substituted for real data when generating the files.

The interesting thing about this flow is that the input can be any of the formats that IDesignSpec takes in, such as, IP-XACT, SystemRDL, CSV, Excel or even Word. The output can be a Word datasheet or a PDF version of it. Looking at an IP-XACT, SystemRDL or even CSV or Excel is not the same as a Word or PDF datasheet. While these formats may be good for machines, they are not always appropriate for human consumption.

View the data sheet.

Generating Counters, Interrupts, Timers using IDesignSpec

System on a chip (SoC) consists of several different microprocessor subsystems together with memories and I/O interfaces. Counters, Interrupts and Timers are a basic building-block of every electronic system. Counter and timer hardware is a crucial component of most embedded systems. A microcontroller may be in-built with one or more timer or counters – to control all counting & timing operations within a microcontroller, count external pulses and also interrupts the processor on a certain count value. Hence, timers/counters and interrupts are widely used concepts in systems.

IDesignSpec consists of many features to include different types of timers, counters and interrupt logic in the design specification. Hence, using IDesignSpec’s counter and interrupt features/properties one can very easily specify counter, interrupt and timer specifications to be used in the design and automatically generate the code for it.

Real-world timer implementations and applications:

Timer blocks are basically digital counters that either increment or decrement at a fixed frequency, which is often configurable, and which interrupts the processor when reaching zero. The timers may have comparison logic to compare the timer value against a specific value, set by software that triggers some action when the timer value matches the preset value.

One special use of hardware timers in computer systems is a watchdog timer. These are designed to perform a hardware reset of the system if the software fails. Synchronous counters are used to create real time clocks. Counters are also used as clock dividers – when on-chip peripherals of the processor works at a lower frequency than the actual frequency of the processor. Most microcontrollers are equipped with one or more precision timing systems that can be used to perform a variety of precision timer functions including generating events at specific times, determining the duration between two events, or counting events.

Counters in IDesignSpec

IDesignSpec uses a bunch of properties to describe the counters. Following paragraphs shows the various forms of counters supported by IDesignSpec.

  1. Counter to count HW events:

t1

  1. Counter to count SW events :

SW read and write events

t2

  1. Counter to count both HW and SW events:

t3

Interrupts in IDesignSpec

IDesignSpec can generate the interrupt circuitry as per the requirements of the design. This is done by specifying additional meta information about the registers that participate in the interrupt generation. The registers are identified as status, pending, enable and mask register.

Interrupt Channels

t4t5

Note : IDesignSpec supports wide range of counter & interrupt properties to describe the behavior of the registers in-respect of counter & interrupt concepts.

Specifying Standard Timers

Following example describes the register Specification of the three 32-bit software programmable timers using TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) using IDesignSpec. Here we are only explaining some complex functionalities of 32-Bit Timer/Watchdog Timer.

User can choose any of the following functionality corresponding to the given spec:

32-bit Timers:

  • 32-bit programmable count down timer.
  • 13-bit prescaler divider.
  • Auto reload option.
  • Generates a single interrupt to the CPU. The interrupt is individually latched to determine which timer triggered the interrupt.
  • Interrupt can be used for DMA event.

Watchdog Timer:

  • 16-bit programmable count down timer
  • 16-bit prescaler divider
  • Lock registers require a specific sequence of keys to enable and change the watchdog settings. These sequence of keys prevent loose pointers from corrupting the state of the watchdog.
  • Generated an active low pulse to the hardware reset when the Watchodg timer expires.

Register Specification Watchdog Timer Registers:

1880h WDKCKLK Watchdog Kick Lock Register 1882h WDKICK Watchdog Kick Register 1884h WDSVLR Watchdog Start Value Lock Register 1886h WDSVR Watchdog Start Value Register 1888h WDENLOK Watchdog Enable Lock Register 188Ah WDEN Watchdog Enable Register 188Ch WDPSLR Watchdog Prescale Lock Register 188Eh WDPS Watchdog Prescale Register

General-Purpose Timer 0 Registers:

1810h TCR Timer 0 Control Register 1812h TIMPRD1 Timer 0 Period Register 1 1813h TIMPRD2 Timer 0 Period Register 2 1814h TIMCNT1 Timer 0 Counter Register 1 1815h TIMCNT2 Timer 0 Counter Register 2

General-Purpose Timer 1 Registers:

1850h TCR Timer 1 Control Register 1852h TIMPRD1 Timer 1 Period Register 1 1853h TIMPRD2 Timer 1 Period Register 2 1854h TIMCNT1 Timer 1 Counter Register 1 1855h TIMCNT2 Timer 1 Counter Register 2

General-Purpose Timer 2 Registers:

1890h TCR Timer 2 Control Register 1892h TIMPRD1 Timer 2 Period Register 1 1893h TIMPRD2 Timer 2 Period Register 2 1894h TIMCNT1 Timer 2 Counter Register 1 1895h TIMCNT2 Timer 2 Counter Register 2

Timer Interrupt Aggregation Register:

1C14h TIAFR Timer Interrupt Aggregation Flag Register

Register List Generated by IDesignSpec

t6

Watchdog Timer Operation:

The Watchdog (WD) timer function is enabled when:

  • The Start Value and Prescale registers have been unlocked.
  • The Start Value and Prescale registers have been programmed.
  • The Watchdog Enable Lock register is unlocked.
  • A 1 is written to bit 0 of the Watchdog Enable register.

t7

The above implemented lock property will make the following RTL code :

t8By the following method we can implement the counter timers which can be used as Watchdog timer or general purpose timer by tweaking functionality:

t9

The above code will generate following RTL hw counter code for both:

t10

The general-purpose timer has a timer interrupt signal. The timer interrupt request is sent to the CPU when the main count register (TIMCNT1 and TIMCNT2) counts down to 0. The same interrupt signal is also routed to the DMAs and can be used as a DMA trigger event.

The TIAFR latches each timer’s interrupt signal when the timer counter expires.

Using following way, we can support interrupt signal:

t11As a consequent of this specification the following code will be generated.

t12

As shown, there will be 3 channels for interrupt which will be OR-ed thereafter to generate an IRQ signal.

To summarize, we have shown how simple and straightforward it is to create a complex Timer/Counter using IDesignSpec features/properties related to Counters, Interrupts, etc. Above, we have taken an example of a simple watchdog timer and highlighted how few striking register-features were easily specified using IDesignSpec’s counter and interrupt based properties. For the detailed information and updates, refer to the online documentation of our IDesignSpec tool or contact support.

 For further information and updates, please refer to the online documentation or send an email to our support team support@agnisys.com.

Creating UVM based environments

Muda (無駄) is a Japanese word meaning “futility; uselessness; wastefulness”.

Since the advent of UVM for design verification, gone are the days of single file environment for verification. These days’ design/verification (DV) engineers have to spend a lot of time managing lots of code in hundreds of files. Understanding the class relationship, the inheritance hierarchy, and the types of various handles, etc. makes the DV engineers less productive.

There was a need of a “smart” editor which would enable DV engineers to write correct-by-construction code and eliminate “muda” from the DV process.

We created DVinsight by bringing together the best that modern technology has to offer. It has been purposefully crafted to be a companion for every DV engineer. It helps engineers to produce the code without coming in the way.

It enables users to write SystemVerilog (SV) following the Universal Verification Methodology (UVM) guidelines.

In this short article, we will show the salient features of this new and exciting tool from Agnisys.

dvi1

Has it ever happened to you that while you are debugging you come across a new class that you have never seen before and you don’t even know where to look for it? You go to the shell, grep the class, sift thru and filter out the class definition, find the file where it is, scroll to the class and now you can review that class. The Quick Edit feature of DVinsight simply does all this at the click of a button.

Quick Edit :- This feature of DVInsight enables you to edit different files quickly by opening an “insight” of files within the same editor and then you can use those insights to edit those files then and there. As shown in the image, if we press Cntrl+E on ‘ambaahb_drv’ then an instance of file where the ‘ambaahb_driver’ class is defined will open in the same editor and then you can edit that file. Note that you can Cntrl+E on any handle or name of the class, or a parameter, or variable, or even a macro. It’s a beautiful thing – one that completely distinguishes DVinsight from other editors.

Folks who use Emacs and Vi/Vim are used to splitting the frame to see sections of the same file or different files simultaneously. DVinsight has this feature too. You can also retain your Vim/Emacs finger memory too while using DVinsight.

Vertical/Horizontal Split :- We can open two files in the same editor at a time by selecting vertical/horizontal split from the menu.

Vim/Emacs mode:- The vim/Emacs lovers would also love this tool as we have provided Vim/Emacs mode. To Enable Vim/Emacs mode from “View>>Enable VimMode/Emacs Mode”.

This is one of the coolest features of DVinsight. The need for this feature comes when you find your self copy pasting same text many times on successive lines, or when you want to select and delete a vertical section from a file.

Multiple Edit/Vertical Edit :- We can edit the same text in multiple lines at the same time using Multiple edits. For using this feature, we will press CTRL and select the lines/places where we want to edit.

The back and forth between the simulator and the editor takes up a lot of valuabe engineer’s time. The inbuilt linting and hinting tool helps avoid these useless round-trips.

DVi-Linting :- This helps you to write DV code correct by construction.

Just keep writing SV/UVM code and on saving your document it’ll analyze your code in the context of the environment and let you know if your code have any error or warning.

DVi-Hint:- Whenever you access any scope in your SV/UVM code, it gets hints from that scope so you need not to open different files just to see name of any member or method.

Going to the shell to execute a compilation command, sifting thru the errors and opening the files and going to the specific line numbers in case of errors is repeated ad-infinitum in a development project. This time is short-circuited by the Shell integrated into DVinsight.

Shell/Command prompt :- A shell is provided to the user where they can run shell commands.
Simulator link:- DVinsight is linked with popular simulators so that user does not have to leave the application, compile the files and come back to the editor to search for errors in the files. On the inbuilt command prompt, run the compilation command. When errors are reported in the files, click on the file name to navigate to the exact location of the error.

There is nothing sweeter than a smart editor that “knows” where you are going.

Auto Indentation:- DVinsight autoindents the code when you save the file.

Auto Code completion:- Code completion happens when you type Cntrl-Space.

Easy code move:- Forget about the boring cut-paste to move your code. Dvinsight provides a better alternative of this. Just select the code you want to move and use Ctrl + Shift + up/down arrow to move your code to desired location.

No need to esacpe your editor and go in your file system to search and open a desired file.

Quick Open:- Press CTRL+SHIFT+O and type the name of the file you want to open

Summary
We have shown how many of the DVinsight features give a very fast paced development environment without coming in the way of code development.

Experts as well as beginners can use the tool with ease. Code created with DVinsight is standardized, which avoids the long and expensive debugging later on in the development process.

Eliminating the wasteful activities of DV engineers means that they can be more efficient in code development.

 For further information and updates, please refer to the online documentation or send an email to our support team support@agnisys.com.