In this paper, we present a design-aware DFT optimization methodology that addresses TCPF (Test Cost Per Fault) hotspots at the source by integrating intelligent Design-Aware Test Points (DATP) directly into the SystemRDL-to-RTL generation flow. Instead of relying on traditional post-RTL structural optimization, the proposed approach introduces ATPG-friendly design enhancements during RTL generation, enabling more efficient testing of automatically generated CSR architectures.

The paper examines the key structural factors that increase ATPG pattern count and manufacturing test cost, including common address buses, deep combinational logic, and complex decode structures within CSR blocks. By optimizing these architectures through automated RTL generation, the methodology improves ATPG efficiency, significantly reduces TCPF hotspots and overall pattern count, and lowers manufacturing test costs while requiring only minimal area overhead. The results demonstrate up to 4X TCPF improvement at the IP level and approximately 50% reduction in ATPG pattern count, making the solution highly scalable for modern SoC designs.

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