In this webinar, we discussed how AI-driven techniques can be applied within verification workflows to automate extraction of design intent, generate UVM components and assertions, and accelerate coverage closure. We also demonstrated how Agnisys AI² leverages AI models to analyze specifications, RTL, and register descriptions to produce structured verification artefacts and guide coverage analysis more efficiently.
Keys takeways:
AI-driven extraction of design intent from specifications and RTL
Automated generation of UVM components and assertions
Faster and more efficient coverage closure using Agnisys AI²
eBook: How Agnisys Eliminates Redundancies in Semiconductor Design, Verification, and Validation
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.
By its very definition, developing a system-on-chip (SoC) device involves both hardware and software. SoCs contain at least one...
Introduction Modern System-on-Chip (SoC) designs are becoming increasingly complex as they integrate multiple processors, accelerators, memory subsystems, and peripherals. Ensuring...
As register maps grow into the tens of thousands of fields, and design teams distribute across geographies, relying on...
