Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

The Agnisys IDesignSpec^TM (IDS) Suite supports clock domain crossings (CDCs) from both the software (SW) and hardware (HW) sides. Techniques used to avoid metastability as signals cross from one clock domain to another include:

• Two-Flip-Flop Synchronizer
• Mux Synchronizer
• Handshake Synchronization

- Write

- Read

- Pulse

• Custom Synchronizer

In a CDC design, one clock is either asynchronous to, or has a variable phase relation with respect to, another clock. Speed and power requirements lead to designs with multiple asynchronous clock domains employed at different I/O interfaces and data being transferred from one clock domain to another.