Agnisys will demonstrate IDS-AI™, the industry’s first agentic AI framework purpose-built for semiconductor development. By combining advanced AI reasoning with Agnisys’ correct-by-construction methodology, IDS-AI helps engineering teams accelerate the journey from golden specification to sign-off.

IDS-AI covers critical stages of the IP-to-SoC development and verification flow, including:

• Specification Checking & Verification – Validate specifications early, identify contradictions and gaps, and improve design accuracy before they become costly silicon issues.
• Assertion Generation – Automatically generate SVA assertions to strengthen design verification, improve coverage, and support formal-ready verification.
• Sequence Generation – Automatically generate UVM test sequences to simplify test development and reduce manual coding effort.
• IP/SoC Sign-off – Streamline verification workflows and provide a connected path from specification through IP and SoC verification to sign-off.

IDS-NoC™: Scalable Network-on-Chip Automation

Agnisys will also showcase IDS-NoC™, a solution designed to eliminate one of the most significant bottlenecks in modern SoC development—building an interconnect fabric that scales efficiently for AI accelerators, automotive systems, and multi-core processors without the timing and integration limitations of traditional crossbar architectures.

Instead of manually designing routers and network interfaces, engineering teams can automatically generate a complete, deadlock-free NoC fabric with virtually unlimited scalability across instances and interconnect blocks. Because the generated RTL is provided as open, plain-text SystemVerilog rather than a black-box implementation, teams retain complete visibility and control over their IP. The result is reduced integration effort, faster time-to-market, and an interconnect architecture designed to support increasingly complex SoC designs.