Semiconductor Design and Verification Articles
January 8, 2024
Streamlining Design Verification with UVM RAL for Efficient Register Access
Explore UVM RAL's versatility for efficient register access in system design. Its dual access paths and integration capabilities streamline verification amidst diverse configurations and growing memory sizes.
December 23, 2023
Deep Dive into UVM Register Model
Uncover the essentials of the UVM register model, its classes, & API. Dive into hardware verification with insights from Agnisys in this comprehensive guide. We'll take a closer look at the UVM Register Model and ...