In this webinar, we showcased how Agnisys IDS-Integrate simplifies and automates the process of IP integration in SoC designs. We demonstrated how IDS-Integrate reduces manual effort and errors by using its TCL and Python-based API to automatically connect IPs based on predefined rules. Key features such as hierarchy manipulation, automatic connectivity, and TGI (Tight Generator Interface) access were explored in detail. Attendees learned how the tool generates RTL and IP-XACT outputs, helping ensure design consistency and significantly accelerating complex SoC development. The session highlighted how IDS-Integrate enhances productivity and accuracy in IP integration workflows.
eBook: How Agnisys Eliminates Redundancies in Semiconductor Design, Verification, and Validation
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.
As I often point out in my blog posts, modern chip development is one of the most complex tasks undertaken...
The semiconductor industry is entering a new phase of engineering transformation. As chip architectures become more complex and AI continues...
Agnisys and Axiomise partner to pair IDS-NoC™ automated NoC generation with nocProve® formal verification for AI, GPU, and inference chip...
