+1 855-VERIFYY
+

Machine Learning Incorporated in IDS NextGen

Machine Learning Incorporated in IDS NextGen

By: | Tags: | Comments: 0

Machine learning has begun to have a huge impact on the EDA Industry. Numerous organizations are heading forward with home grown machine learning algorithm in order to make specification better.

Agnisys is making headway with home-grown machine-learning algorithms — and applying it to IDS NextGen  multi platform product which helps user to create SoC specification at an enterprise level.

It handles individual IP to sub-system to SoC level and is compatible with Word ,Excel, IP-XACT, RALF, CSV, System RDL. IDS NextGen generates  design and verification code for not  just registers but sequences in one integrated environment. It reduces the verification time by generating the entire UVM SV and SystemC output Sequences.

The NextGen product attempts to “understand” the specification using Machine Learning technology and guides the user about issues with the specification. It helps create a standardised specification. Capturing issues in the specification is the extreme form of “Shift-Left” that the industry has been seeing. Agnisys motto is to stop issues from germinating in the first place so that less time is spent on the debug - which is often very costly.

Once the specification is entered, user can create custom outputs using a template engine. IDS now supports all current prevailing input and output formats.

The NextGen product also supports special safety and reliability requirements for Automotive and IoT sectors.

Discover what’s new - IDS Next Gen

Comprehensive SoC/IP Specification and Code Generation Tool

  • Behavior Driven, Spec Centric Development

  • Single multi-platform UI product which helps user to create SoC specification at an enterprise level

  • Promotes reuse and collaboration

  • Inbuilt DRC checks improve design quality

  • Inbuilt machine learning algorithms for guidance

  • Handles individual IP, sub-system to SoC level

  • Compatible with Word ,Excel, IP-XACT, RALF, CSV, System RDL.

  • Generates  design and verification code for not  just registers but sequences

  • Reduces the verification time by generating UVM SV, SystemC

Hence there are multiple opportunities and  untapped resources in the EDA industry with respect to machine learning. By turning mountains of raw data into valuable design insight, machine learning gives EDA a desperately needed shot in the arm.

 

Leave a Reply