With the growing requirement for configurable IP, processor and SoC, the number of registers, access type and interrupts have gone up for the last few years and aggravated the complexity of designs. For example, a design with just 100 addressable registers of 32 bits would add up to 100*2^32 fields and any wrong implementation of data or wrong configuration would cause trouble. Also, registers are widely used in the SoC peripherals like – DMA, UART, PCI, MIPI, Display, Audio, Ethernet etc. It takes a great deal of time and effort for defining registers for the peripherals. To optimize the resource, quality and project delivery schedule, using controllable automation is a prudent choice.
Agnisys will showcase its product IDesignSpec™ in ARM® TechCon 10-12 Nov 2015 at Santa Clara, CA. It helps to generate the Registers, FIFOs, Register access, Interrupts, virtual registers, descriptors and Sequences – for ARM-based projects.
Agnisys announced the enhanced capability of IDesignSpec for defining registers interfaced with the ARM AMBA® bus interface standard compliance for the configurable IP and SoC design. The latest added features will help ARM designers / architects to create executable specs for the HW/SW interface at an early stage when the business spec is being worked on, and subsequently generate required output for the design & verification phase. The executable specs are easy to write and understand, and give freedom to choose multiple formats. That is, the specifications can be written in MS Word, MS Excel, OpenOffice Cal with IDesignSpec editor Plugin or text based industry standard formats like SystemRDL, RALF, IP-XACT. IDesignSpec generator takes the specifications and builds the synthesizable RTL code, SV-UVM model, C/C++ headers and the documentation in HTML, Word, and PDF formats.
The specification captures the hierarchical structure of the designs, and let users define registers, register blocks, references to the register blocks or even references to the other register specification files. Any change required in the functionality can be included in the specs and modified output can be generated. IDesignSpec also offers the assistance to the verification team by generating the verification environment for the registers & memory banks and their interface to the AMBA buses.
ARV™ is an add-on product to IDesignSpec that expands an already powerful register specification solution with capability to automate the register specification-creation-verification process for ARM-based SoCs, IP and FPGA semiconductor projects. ARV saves semiconductor teams time and improves quality by enabling complete code coverage for design registers that are the key integration point for semiconductor design, IP, software and interfaces. ARV-Formal uses formal tools such as Mentor Questa® Formal and OneSpin’s DV-Verify 360™ to ensure that Register operations conform to the user specification and ARM standards. ARV-Sim can use Mentor Graphics’ Questa® VIP to create a UVM based simulation environment to verify the registers automatically.
About Agnisys- Agnisys provides IDesignSpec for specification driven system development for ARM-based designs. Client IP for AMBA buses such as AXI, APB, AHB AXI4LITE, AHB3LITE can be generated using IDesignSpec. Along with synthesizable IP code, a verification test environment, a software API and documentation is created as well. Agnisys has established itself as leading Electronic Design Automation (EDA) supplier with more than 500 users worldwide. Its products use patented technology and provide intuitive user interfaces with high-end technology underneath. As a result, Agnisys’ products are now de-facto standards in many industry verticals e.g. Defense and Avionics.
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