ISequenceSpec Automatically Generates Sequence for Verification, Firmware Validation Used From Early Design Through Post-Silicon Validation
LOWELL, MA–(Marketwired – May 24, 2016) – Agnisys, provider of a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation, today announced availability of a portable sequence generator usable from early design and verification to post-silicon validation.
Patent-pending ISequenceSpec™ enables users to describe programming and test sequences of a device once and generate sequences automatically. It provides a straightforward specification format to describe the sequences and generates the code that ensures synchronization between verification to validation. Users describe initialization, configuration and test sequences and ISequenceSpec automatically generates Universal Verification Methodology (UVM) models and firmware sequences usable throughout the system development process.
Sequences are a set of steps to achieve certain functionality that involves writing or reading specific bit fields of the registers or memory in a SoC or IP block. The same set of steps formerly required a manual rewrite, leading to inconsistencies and incorrect or inexact information.
“Agnisys automated the painstaking and error-prone effort of manually coding sequences in a variety of languages and environments,” affirms Anupam Bakshi, Agnisys’ chief executive officer. “Users can enter the sequence of an operation in the form of a common specification and ISequenceSpec will convert that into a portable sequence library for a variety of domains.”
Sequences use register information in any format supported by Agnisys’ IDesignSpec, register specification creation and generator software, including industry standards IP-XACT, SystemRDL and RALF, or custom formats, such as CSV or XML, Word or Excel. Users are able to create a library of sequences targeted to the language to be chosen by the Accellera Portable Sequence Working Group (PSWG).
ISequenceSpec can generate sequences that can be imported into the Cadence® Perspec™ System Verifier, an automated system-level coverage-driven test development tool, and Mentor Graphics’ Questa® inFact™ testbench automation solution.
“Agnisys’ new ISequenceSpec is designed to meet growing market interest for tools that augment portable test and stimulus automation,” says Larry Melling, product management director at Cadence. “The goal is to save time by automating generation of register-level sequences in either UVM or firmware required to initialize and program IP blocks. Cadence’s Perspec System Verifier works with ISequenceSpec to simplify the generation of complex subsystem and system-level design and further improve engineering productivity.”
“I am pleased to see our partnership continues to yield results with the most recent addition of automatic sequence generation by Agnisys’ ISequenceSpec that can be imported into our Questa inFact testbench automation solution,” remarks Dennis Brophy, director of strategic business development, Mentor Graphics Corporation. “This is a productivity boost for SoC designers as it helps eliminate costly mistakes and reduces time-to-market pressures.”
ISequenceSpec joins a growing portfolio of versatile software from Agnisys for SoC design and verification including, register generation, design verification and documentation automation. Agnisys will exhibit at the Design Automation Conference (DAC) in Booth #420 Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.
Pricing and Availability
ISequenceSpec works on 32- and 64-bit Unix, Linux and Windows operating systems. It is shipping now. Pricing is available upon request.
Agnisys Inc. has established itself as a leading Electronic Design Automation (EDA) supplier of innovative software to solve complex design and verification problems for system development with certainty. Its products provide a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation. Based on patented technology and intuitive user interfaces, they increase productivity and efficiency while eliminating system design and verification errors. Founded in 2007, Agnisys is based in Lowell, Mass., with R&D centers in the United States and India. Phone: (855) 837-4399. Email: firstname.lastname@example.org. More information about Agnisys can be found at: www.agnisys.com
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Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.