In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars on how specification automation benefits many teams developing intellectual property
Read moreIt’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a
Read moreRegister-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and verification. Today’s designers operate very differently than their predecessors who
Read moreIdentifying the challenges in moving from a static spec to a live one.
We all want our creations to transcend time. Our products, our
Read moreSomewhere in the deep trenches of a UVM based verification project, an engineer teeters on the verge of insanity.
As the saying goes, the faint of heart
Read moreIn our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If we take a look at the AMBA®AXI4Lite bus protocol, it
Read moreMoore's law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of
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