How to Automatically Generate Better IC Design Registers
There is probably no component more ubiquitous across integrated circuit (IC) and intellectual property (IP) designs than registers. Addressable registers
November 8, 2023
Efficient System-Level Verification: UVM and Embedded C/C++
As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate
Three Steps to Set Up a RISC-V SoC UVM Testbench
Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one