view-page-idesignspec-gdi-for-safety-critical-designs

Webinar: IDesignSpec GDI for Safety-Critical Designs

In this webinar we discussed how the IDesignSpec GDI FS tool helps teams to develop Functionally Safe designs.

We hope you enjoy the webinar.

eBook: How Agnisys Eliminates Redundancies in Semiconductor Design, Verification, and Validation

Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.

Automatic Generation of a Network-on-Chip Interconnect

ByAgnisys August 24, 2026 Semiconductor Design & Verification

As the art of chip design began to mature, interconnecting major blocks required more than just ad hoc collections of signals...

Figure 1 AXI4 NoC (4 Initiators and 12 Targets)

IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design

ByAgnisys August 10, 2026 Semiconductor Design & Verification

Introduction As SoC designs continue to grow in complexity, the communication infrastructure connecting various IP blocks becomes increasingly important. Traditional...