agnisys offers a year in review
January 3, 2023

Taking Stock of the Past Year

As we transition into 2023, it’s a good time to look back over the past year and assess it, much as I did a year ago. Anupam Bakshi offers thoughts on 2022

Tool Qualification Kit for Functional Safety Compliance
June 28, 2022

Tool Qualification Kit for Functional Safety Compliance

With growing advancements in hardware designs, the complexity of designs has increased multiple folds and brought great challenges to the lifecycle of quality management, development, validation, verification, and ...

Tight Generator Interface support in SoC-E
June 28, 2022

Tight Generator Interface support in SoC-E

As per IP-XACT User Guide, IP-XACT defines an API called Tight Generator Interface (TGI) to query, modify, create, and delete IP-XACT XML documents. The standard defines this API in terms of SOAP (Simple Object Access ...

Chip-in-Chip support for multiple input format
June 28, 2022

Chip-in-Chip support for multiple input format

Introduction  IDesignSpecTM supports multiple design hierarchies like “chip”, and “block” to enable different architectural design flows.  A block can contain registers. A chip can contain other blocks and provide an ...

Formal Verification through ARV-Formal™
June 28, 2022

Formal Verification through ARV-Formal™

As the ASICs are getting larger and more complex, the netlist simulation is becoming a veritably time-consuming process, and it isn’t worth running weeks of netlist simulations corresponding to a veritably small change ...

Automating UVM-Based IP and SoC Functional Verification
June 24, 2022

Automating UVM-Based IP and SoC Functional Verification

Ask a bunch of engineers about the Universal Verification Methodology (UVM) and you’ll hear two distinct sets of responses, sometimes from the same people. Most verification engineers agree that UVM was a huge leap in ...

What’s Next in Specification Automation
April 25, 2022

What’s New and What’s Next in Specification Automation?

Over the last few months, I’ve primarily shared two kinds of posts on this blog. The Design Automation Conference (DAC) in December and the transition to the New Year prompted me to look back at how much Agnisys has ...

Agnisys – Certified Safe for ISO 26262 Design
April 6, 2022

Agnisys – Certified Safe for ISO 26262 Design

Agnisys has customers designing all sorts of intellectual property (IP) blocks, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and system-on-chip (SoC) devices across a wide ...

A Standard way to build IPs and SoC using IDesignSpec and IP-XACT
March 22, 2022

A Standard way to build IPs and SoC using IDesignSpec and IP-XACT

A Standard way to build IPs and SoC using IDesignSpec and IP-XACT

Expanding the Scope of Specification Automation
March 12, 2022

Expanding the Scope of Specification Automation

Late last year, I published a blog post that summarized what had transpired for Agnisys over the course of 2021. That was an occasion to think about how much our company and our products have expanded over time. A few ...

Specification Automation for Embedded Programmers
January 31, 2022

Specification Automation for Embedded Programmers

As an electronic design automation (EDA) company, Agnisys provides many benefits for chip design and verification engineers. Our specification automation solution generates both the register transfer level (RTL) design ...

Next Generation SystemRDL
January 22, 2022

Next Generation SystemRDL - Using IDesignSpec for register implementation

Typically thousands of registers are required for today’s complex designs, which are used to control the operations of the SOC.

Winding Up an Eventful Year
December 24, 2021

Winding Up an Eventful Year

As we close in on the final days of 2021, I can’t help but think back over the events of the year and offer a few observations. At the front of my mind is the recent Design Automation Conference (DAC) in San Francisco. ...

Welcome Back to DAC
November 30, 2021

Welcome Back to DAC – in Person – in San Francisco

Most engineers involved in the design, verification, and validation of electronic systems are familiar with the Design Automation Conference (DAC). It’s the stimulating combination of a highly technical conference with ...

An Update on Functional Safety and ISO 26262
October 29, 2021

An Update on Functional Safety and ISO 26262

Just about a year ago, I published a blog post about the emerging need for better functional safety and security in a wide range of electronic products. We recently held a webinar on functional safety and how we enable ...

Sequence Verification with UVM and Embedded C/C++
September 23, 2021

System-Level Register and Sequence Verification with UVM and Embedded C/C++

As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate the SystemVerilog RTL design, Universal Verification Methodology (UVM) ...

Specification Automation for Formal Verification
August 14, 2021

Specification Automation for Formal Verification

I hope that you’ve been able to attend or watch the recordings of the sessions in our latest webinar series on specification automation. We’re focusing on the requirements for different project teams and different tasks ...

Automating Your Documentation Flow
July 19, 2021

Automating Your Documentation Flow

In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars on how specification automation benefits many teams developing intellectual property (IP) blocks and system-on-chip (SoC) ...

Specification Automation for Designers
June 23, 2021

Specification Automation for Designers

If there’s one good thing to emerge amid all the challenges of the last year and a half, it’s improved technology for remote learning. On-line talks, webinars, and podcasts are nothing new, but with so many people ...

Setting a High Standard for Standards-Based IP
May 31, 2021

Setting a High Standard for Standards-Based IP

In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has proven to be quite popular with our users, and that’s not surprising. Reuse plays a big role in ...

Automating the UVM Register Abstraction Layer (RAL)
April 27, 2021

Automating the UVM Register Abstraction Layer (RAL)

It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a few advanced ...

Automating IP and SoC Development
March 25, 2021

Automating IP and SoC Development

The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed in my last post, we held our first Agnisys User Group Educational Roundtable (AUGER) on March 18. We had a great ...

AUGER: Celebrating Our Users
February 12, 2021

AUGER: Celebrating Our Users

In my last post, I discussed the importance of partners to the EDA industry in general, and to Agnisys in particular. Partnerships exist because our users demand them. In today’s post I’d like to focus on a group even ...

Why Users Care about EDA Partnerships
January 26, 2021

Why Users Care about EDA Partnerships

Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular. When I thought about writing a blog post on this topic, I asked myself whether this might be of ...

Functional Safety and Security in Embedded Systems
November 17, 2020

Functional Safety and Security in Embedded Systems

Electronics in general, and embedded systems in particular, become more critical every day. There is hardly a single aspect of our lives that is not controlled, monitored, or connected by embedded systems. Even ...

A Unified Flow for Embedded Systems Development
October 28, 2020

A Unified Flow for Embedded Systems Development

Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual Design Automation ...

Automatic Handling of Register Clock Domain Crossings
October 15, 2020

Automatic Handling of Register Clock Domain Crossings

Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and verification. Today’s designers operate very differently than their ...

AI-Based Sequence Detection for IP and SoC Verification and Validation
September 28, 2020

AI-Based Sequence Detection for IP and SoC Verification and Validation

A couple of years ago at the Design Automation Conference (DAC), as I walked the exhibit floor I was amused by how many EDA vendors had jumped on the marketing bandwagon for artificial intelligence (AI) and machine ...

Specification-Driven UVM Testbench Generation
September 22, 2020

Specification-Driven UVM Testbench Generation

In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world of semiconductor ...

The Next Generation of Register, Sequence, and SoC Automation
August 28, 2020

The Next Generation of Register, Sequence, and SoC Automation

Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification, you can generate ...

Automating IP Design and Verification
August 16, 2020

Automating IP Design and Verification

In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators (SLIP-G™), and IDS NextGen™ (IDS-NG) ...

A Quick Look Back at a Virtual DAC
August 4, 2020

A Quick Look Back at a Virtual DAC

Recapping a virtual event where new solutions were unveiled.

DAC May Be Virtual, but Our New Products Are Not
July 18, 2020

DAC May Be Virtual, but Our New Products Are Not

Anyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference (DAC). This event dates back 57 years, a long time for anything to last in our high-tech world. ...

Smart Assembly of SoC Designs
June 30, 2020

Smart Assembly of SoC Designs

System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design, and verification are all challenging. This blog post focuses on the ...

RISC-V SoC UVM Testbench
June 17, 2020

Three Steps to Set Up a RISC-V SoC UVM Testbench

Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides a ...

Automation of the UVM Register Abstraction Layer
May 28, 2020

Automation of the UVM Register Abstraction Layer

A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the key ...

Doing What We Can in Challenging Times
May 9, 2020

Doing What We Can in Challenging Times

Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But few of us have experience dealing with a challenge as broad and disruptive as the COVID-19 global ...

Correct-By-Construction SystemVerilog UVM Testbenches
April 23, 2020

Correct-By-Construction SystemVerilog UVM Testbenches

Modern RTL design verification (DV) environments are both very powerful and very complex. They include advanced simulation testbenches plus support for formal verification, virtual prototypes, and emulation technology. ...

New Methods For Faster Development
December 9, 2019

Adopting New Methods For Faster Development Of RISC-V based SoCs

The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course, the various technologies for the automotive industry has led to a new ...

Creating Test Sequences for RISC-V Cores and SoCs
October 7, 2019

Creating Test Sequences for RISC-V Cores and SoCs

By Louie De Luna, Agnisys Chief Product Evangelist The idea of an open-source CPU core was virtually unheard-of ten years ago – let alone using it for commercial applications. The CPU core has been the most critical ...

Repurposing von Neumann Architecture with SRAM-based Register Files
August 11, 2019

Repurposing von Neumann Architecture with SRAM-based Register Files

By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades, but with the advent of AI applications and big data the entire ...

Not your Average UVM Testbench Generator
May 20, 2019

Not your Average UVM Testbench Generator – Unveiling at DAC 2019

By Louie De Luna, Agnisys Chief Product Evangelist Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t really appreciate the impact of the ...

EDA Is Advancing
April 15, 2019

EDA Is Advancing – but Where Are the Women?

By Ishanee Bajpai – Senior Marketing Executive, Agnisys 1981 marked the beginning of EDA as an industry. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.  As the ...

Setting the Stage for the Next Abstraction
March 26, 2019

Setting the Stage for the Next Abstraction

By Louie De Luna, Agnisys Chief Product Evangelist As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to schematics to ...

Register Automation using Machine Learning
February 17, 2019

Register Automation using Machine Learning

By Louie De Luna, Agnisys Director of Sales and Marketing Right after Google’s AlphaGo system defeated a human Go world champion in 2015, the hype of deep learning and machine learning (ML) was quickly assimilated into ...

Where Tool Ideas Come From
January 21, 2019

Where Tool Ideas Come From – A Case for a Portable Sequence Generator

By Louie De Luna, Agnisys Director of Sales and Marketing Tools are made to automate a process, perform calculations, minimize errors and improve efficiencies, but at their core, tools are made to solve a given problem. ...

Top 2018 Agnisys Resources
December 17, 2018

Top 2018 Agnisys Resources

Every year we take a look back at the resources we’ve created to determine what you’ve found most useful. We invite you to take a look below at our top viewed and downloaded resources from 2018. RECORDED ...

Automating Register Verification
December 3, 2018

Automating Register Verification with 100% Functional Coverage

 By Louie de Luna, Agnisys Director of Sales and Marketing UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics ...

What ARE the Root Causes of Functional Flaws?
October 30, 2018

What ARE the Root Causes of Functional Flaws?

By Louie de Luna, Agnisys Director of North American Sales and Marketing Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. ...

Out of the Office
August 24, 2018

Out of the Office – Lessons from a client visit in Edinburgh

As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a bit of tunnel vision as we busy ourselves with client meetings, conferences, socializing with potential new clients, ...

DAC 2018 Review with Anupam Bakshi
July 10, 2018

DAC 2018 Review with Anupam Bakshi, CEO – Emerging must-have toolset in System Development

This was an intriguing DAC. Hardware-Software Interface (HSI) is increasingly emerging as an area of importance, and because of this Agnisys has begun to emerge as a must-have toolset in the system development ...

Duolog format for IDesignSpec create executable design code from the specification
June 25, 2018

Agnisys now supports Duolog format for IDesignSpec create executable design code from the specification

With the ability to read in the Dulog format, users can create code from a specification and experience faster RTL and more versatile UVM.

Teaching the computers to teach themselves
June 11, 2018

Teaching the computers to teach themselves

Why Machine Learning Matters Machine learning (or “ML” for short) may have begun life as something of a buzzword, but it has long since proven itself to be anything but. At its core, the term itself describes a ...

How safe is your ride?
May 28, 2018

How safe is your ride?

The Intersection of Functional Safety and Electronic Design In an industry that has gone through an incredibly rapid transformation over the past few years alone, auto manufacturers all over the world have had to ...

Verification Sequences
May 17, 2018

shift_left (Validation Sequences) = Verification Sequences

Verification and Validation are two sides of the same coin In 2011, Intel discovered a design flaw in its Sandy Bridge combination graphics-microprocessor chip that led to not only a major production delay but that ...

An excerpt from our experience at DVCon 2018
May 17, 2018

An excerpt from our experience at DVCon 2018

Participating in DVCon has always been a wonderful experience for us as an organization. We had a great response and superb interaction with some of the most amazing leaders from the semiconductor industry. We were ...

A Standard way to build IPs and SoC using IDesignSpec and IP-XACT
May 10, 2018

IDS NextGen – Comprehensive SoC/IP Specification and Code Generation Tool

I’m yet to meet a person who doesn’t like simplicity in engineering. I do believe that   Electronic Design Automation (EDA) products should be designed in an elegant way,     with minimum over-reach. They should let the ...

IDesignSpec NextGen at DVCON 2018
February 12, 2018

Agnisys to showcase IDesignSpec NextGen at DVCON 2018

Agnisys will showcase IDesignSpec NextGen – the Next Generation product for  capturing requirement specification for embedded designs, and automatically  generating code from it. IDS NextGen is a multi-platform product ...

Inroads into EDA using Machine Learning
February 5, 2018

Inroads into EDA using Machine Learning

Machine Learning (ML) is the rage these days and we were not untouched by it. Being immersed in Specifications and dealing with customer queries about register and   sequence specification on a daily basis, we thought, ...

Machine Learning Incorporated in IDS NextGen™
January 23, 2018

Machine Learning Incorporated in IDS NextGen™

Machine learning has begun to have a huge impact on the EDA Industry. Numerous organizations are heading forward with home grown machine learning algorithm in order to make specification better. Agnisys is making ...

Consolidation in Semiconductor Industry
November 20, 2017

A pragmatic approach towards transformation – Consolidation in Semiconductor Industry

Consolidation is a not a totally new phenomenon for semiconductor Industry. Although the industry has shown no consolidation through almost all its history and or 30 to 40 years, semiconductor companies enjoyed a huge ...

Different flows for UVM Register Generation
May 24, 2017

Different flows for UVM Register Generation

The UVM register model is an essential component of the UVM based verification for modern designs. In this article we discuss the various paths to create UVM register model. We at Agnisys help teams automatically ...

Circle of Work Life
February 21, 2017

Circle of Work Life

In engineering, we often go about our work not knowing how that work touches others’ life and society in general. However, when you come to know about the impact this work has created, it is quite gratifying and ...

MAC and Linux GUI requirements
February 9, 2017

Addressing MAC and Linux GUI requirements for Register and Memory Map Specifications

We all have different tastes, different habits and when it comes to work we like to work in different environments using different operating systems, different code editors with our favourite set of tools. In the ...

Growth in Design Verification Consulting Services
November 24, 2016

Growth in Design Verification Consulting Services

After almost a decade of focusing on SV, UVM, SystemC to build software products and teaching advanced verification/modeling to hordes of professionals, Agnisys has launched its consulting division to address the dire ...

Streamlining FPGA Design
July 7, 2016

Streamlining FPGA Design from Specification to Bitstream

Hardware is verified using simulators. Software compiled and debugged using compilers and debuggers. When it comes to the hardware/software interface, it’s not so straightforward. The FPGA development process can be ...

Ongoing Semiconductor Industry Challenges
July 7, 2016

Ongoing Semiconductor Industry Challenges

The Design Automation Conference is over for the year. Attendee leads or inquiries, to be more precise, have been collected and booths stored away for next year. The EDA industry has left the Austin Convention Center.   ...

It’s All In The Sequence
May 27, 2016

It’s All In The Sequence

Whether dealing with SoCs or a disaster in space, determining the correct set of steps is vital. No project team wants a “Houston, we have a problem,” moment. And yet, they happen all too frequently, even though there ...

Making Way For Register Specification Software
May 5, 2016

Making Way For Register Specification Software

While more registers means more functionality and configurability, more is not always better. No one gives much thought to the heating, ventilation and air conditioning registers in the house–typically, two in each ...

The Ultimate Shift Left
April 11, 2016

The Ultimate Shift Left

Important observations from Einstein and New England’s ice traders.. Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several ...

Portable Stimulus Resonated
March 16, 2016

Tales from the DVCon 2016 – Portable Stimulus Resonated

The DVCon Conference this year, was quite eventful for us with a lots of visitors at our booth. We were excited about the interest shown for IDesignSpec™ and our new product ISequenceSpec™ (ISS) – “Portable Sequence ...

2015 Year End review
December 30, 2015

2015 Year End review – DV Challenges

Wow what a marvelous year 2015 has been to Agnisys, with full of events at the various technical exhibitions, new customers, new features and new products and not to forget – new partnership. It would be unfair to say ...

Musings from ARM TechCon Santa Clara 2015
December 9, 2015

Musings from ARM TechCon Santa Clara 2015

The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but a few who were genuinely interested in Agnisys. Since it was our first foray into ARM TechCon, it was good to meet new set of ...

Does UVM sometimes make you feel stupid?
September 21, 2015

Does UVM sometimes make you feel stupid?

Somewhere in the deep trenches of a UVM based verification project, an engineer teeters on the verge of insanity. As the saying goes, the faint of heart need not attempt UVM based verification. But what makes it so ...

IDesignSpec generated IP
July 22, 2015

Questa® VIP validates IDesignSpec generated IP

In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If we take a look at the AMBA®AXI4Lite bus protocol, it has different channels for ...

Semiconductor Data Sheet Automation
July 11, 2015

Semiconductor Data Sheet Automation – Just The Way You Want It

Moore’s law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of technology. But, along with this, a new complexity takes shape in the form of documentation for ...

Electronic Design Automation Trade Show Update – 52DAC
June 27, 2015

Electronic Design Automation Trade Show Update – 52DAC

Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher levels of productivity. I find that interesting as we at Agnisys have been doing this left shift since ...

Automatic Register Verification Gains Acceptance at DAC
June 14, 2015

Automatic Register Verification Gains Acceptance at DAC

With the Design Automation Conference wrapping up this week in San Francisco, there is one thing we can say for sure – Automatic Register Verification (ARV) gains acceptance with design and verification teams. Last ...

Create Complex Registers in IDesignSpec
May 28, 2015

How To Create Complex Registers in IDesignSpec

We talk about creation of complex registers in IDesignSpec, generation of their suitable RTL and UVM models. The Software addressable registers in your design do not always just have simple read-write access. Sometimes ...

Advancing Productivity for SystemVerilog
April 26, 2015

DVinsIght-Pro Version 2.0 Advancing Productivity for SystemVerilog Universal Verification Methodology (UVM) Verification Code Development

Agnisys just released DVInsight-Pro version 2.0 with many new features that enable much more productive SV/UVM code development. Do you feel lost when you are facing UVM code? Do you have to sift through hundreds of ...

Semiconductor Register Specification
March 4, 2015

Semiconductor Register Specification: Shadow of a Shadow

So we have been working in the register specification space for a long time. We came out with the IDesignSpec tool around 2010. Five years of constant refinement and evolution based on the customer feedback has created ...

IDesignSpec for The TOTEM Experiment Project
December 10, 2014

CERN Selects IDesignSpec for The TOTEM Experiment Project at the Large Hadron Collider

The Large Hadron Collider (LHC) at CERN is the worlds largest and most powerful particle accelerator. This research facility enables some of the most advanced scientific experiments.  The TOTEM experiment is dedicated ...

DVCon Europe Needs Automatic Register Verification and Generation
October 30, 2014

DVCon Europe Needs Automatic Register Verification and Generation

I feel like a bumblebee, going from the DVCon in US, to the next one in India to then to Europe.  All this cross-pollination is exciting and enriching when experiencing the needs of the Semiconductor design engineers ...

DVCon India takes off
September 26, 2014

DVCon India takes off!

DVCon had a solid start in Bangaluru, India.  The audited attendee numbers will be coming in later, but we believe we had approximately 425+ delegates. That is truly amazing for the first year of the event! For me, it ...

Getting Ready for DVCon India 2014
September 24, 2014

Getting Ready for DVCon India 2014

It is penultimate day – the day before the big event! Preparing and launching the first ever DVCon India event feels like taxiing a plane down the runway, ready to take off.  It is new; the design was replicated from ...

What Every Engineer Should Know About SoC Register Generation
July 17, 2014

What Every Engineer Should Know About SoC Register Generation

Register Generation is a Must-Have Capability Today’s SoC designs contain several thousands of registers and memory map elements. The design team must, from the architecture, create the register and memory map ...

Reduce SV/UVM Implementation Time
July 17, 2014

The 5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

Modern SoCs get more and more complicated each and every day.  As the complexity of modern electronic semiconductor device design increases, niche tools for every nook and cranny of the design process emerge to help ...

Presenting DVinsight
June 5, 2014

DAC Day 3: Presenting DVinsight, Universal Verification Methodology IDE

Ending the last day of DAC strong with a presentation of DVinsight, a Universal Verification Methodology IDE The highlight of the last day at DAC was my presentation at the verification academy booth.  I presented ...

System On Chip Design Challenges Addressed by Agnisys
June 4, 2014

DAC Day 2: System On Chip Design Challenges Addressed by Agnisys

System on Chip Design Challenges – The Highlight of DAC Day 2 It was a very busy day for Agnisys on the second day of the Design Automation Conference. On day two, we learned how much our products address System on Chip ...

Universal Verification Methodology Adoption
June 3, 2014

DAC Day 1: Universal Verification Methodology Adoption – Lots of Room to Grow

The first day of the Design Automation Conference for Agnisys was exciting.  We experienced a higher traffic flow than Monday during previous years.  This picture shows our booth at the DAC conference.   For those of ...

In preparation for DAC 2014
May 8, 2014

In preparation for DAC 2014

As an EDA company our development cycle seems to revolve around DVCon and DAC. This year DVCon and DAC came fairly close together. I feel, we just finished DVCon and now we are preparing for DAC. Come to think of it, ...

DVCon 2014 wrap-up
March 14, 2014

DVCon 2014 wrap-up

DVCon 2014 was a wrap. It was marked by record attendance and participation both by the DV Community and the exhibiting vendors. Enthused, the Accellera team is now forging new frontiers with the DVCon brand name into ...

DVCON 2014
February 5, 2014

DVCON 2014: Strong Focus on both, Design & Verification

Here we go! The Design and Verification Conference (DVCON 2014) is round the corner. Make sure you register for the event which has been one of the premier conferences for IC design and verification engineers. This ...

EDA Companies must Collaborate or Die
September 10, 2013

EDA Companies must Collaborate or Die

Recently at the sidelines of DAC, Anupam Bakshi, CEO of Agnisys, Inc. sat down with Karen Bartleson, Director of Community Marketing at Synopsys to discuss a very important topic that is close to the heart of the ...

Using IVerifySpec to test IDesignSpec
May 28, 2013

Using IVerifySpec to test IDesignSpec: A case of doctor eating his own medicine!

IDesignSpec generates several outputs from a single spec. We started out as a simple tool that just dealt with registers. After 6 years the tool has metamorphosed into an Executable Spec tool for Digital design. This ...

Complete Register Design Automation
May 28, 2013

IDesignSpec Provides Complete Register Design Automation

Published on 05-19-2013 07:30 PM in Semiwiki It goes without saying that registers play a vital role in designing any ASIC, FPGA, SoC or System. In today’s world, while designing SoC with multiple IPs and ...

Agnisys makes Design Verification process extremely efficient
May 28, 2013

Agnisys makes Design Verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs ...

Begin Initialization Sequence
December 7, 2012

Begin Initialization Sequence – 10, 9, 8, …

Launching new capability to specify Sequences in IDesignSpec

Customer’s Music and DVCon 2012
March 14, 2012

Customer’s Music and DVCon 2012

The buck stops at the CEO. DVCon 2012 happenings from our perspective.

Are assertions difficult?
March 5, 2011

Are assertions difficult?

So the cat is out of the bag. We are working on an assertion tool. This DVCon we turned quite a few heads when we announced our new assertion product IAssertSpec. Not that the tool is ready by any stretch of the ...

Age of cooperation, is it?
November 24, 2010

Age of cooperation, is it?

It's heartening to see greater cooperation between various EDA companies, both big and small. The ongoing work under Accellera for UVM, UCIS and IP-XACT is testament to this fact.  It is often bemusing to see the push ...

5 tips to speed up regressions
September 22, 2010

5 tips to speed up regressions

This article lists out ways to improve regression run time for hardware design verification.

#47DAC musings
June 19, 2010

#47DAC musings

Going to DAC had a boosting effect on us.

It's DAC time of the year again
June 6, 2010

It's DAC time of the year again!

Started blogging again, this time from our own blogging site. Its DAC time of the year again. This will be our 2nd year in a row at DAC. Hopefully we have learned from our mistakes and won’t be repeating them this year. ...

Great turnout at the Design Automation Conference
July 28, 2009

Great turnout at the Design Automation Conference

We had a great first day at DAC. All the talk about recession and economic doom were hard to believe. People were enthusiastic and upbeat. Even the guys and gals looking for work were upbeat and were considering it to ...

First sale is always sweet
June 17, 2009

First sale is always sweet!

I’m thrilled. Finally, we have a customer who sees the value that IDesignSpec brings for his company. We are indeed thankful to them for trusting our technology. I think this is validation of the concepts on which this ...

Is cheap EDA tool an oxymoron?
May 25, 2009

Is cheap EDA tool an oxymoron?

Business schools teach us that the way to set the price on a product has nothing to do with the cost. You sell it at a price that the market can afford. Semiconductor industry was able to afford heavy price tags on EDA ...

Why is it difficult to make your first EDA tool sale?
April 25, 2009

Why is it difficult to make your first EDA tool sale?

As you know we have created a brand new EDA tool that saves people a lot of time and money. Ok you have heard that before. But this is real 🙂 Ok so you have heard *that* before too! So how do I convince you to take a ...

IDesignSpec
April 24, 2009

IDesignSpec: An Engineering tool with a difference.

I’m so excited … After years of work, my team and I have converted a word processor into an Engineering tool. Its like the Gene in Arabian Nights who says ” your wish is my command” … except in this case, your word is ...