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How to Automatically Generate Better IC Design Registers

There is probably no component more ubiquitous across integrated circuit (IC) and intellectual property (IP) designs than registers. Addressable registers...

Efficient System-Level Verification: UVM and Embedded C/C++

As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate...

Three Steps to Set Up a RISC-V SoC UVM Testbench

Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one...

Integration is Key for the Adoption of Specification Automation

I frequently delve into the solutions Agnisys offers for the seamless generation of design, SoC verification, testing, software, validation, and...

Automation of the UVM Register Abstraction Layer

A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based...

A Unified Flow for Embedded Systems Development

Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC)...

Functional Safety and Security in Embedded Systems

Overview Electronics in general, and embedded systems in particular, become more critical every day. There is hardly a single aspect...

Effective Smart Solutions for Standards-Compliant SoC and IP Verification and Development

In the realm of semiconductor development, often characterized by its pioneers, cowboys, shootouts, gamblers, and gunslingers, one might be tempted...

AI-Based Sequence Detection for IP and SoC Verification & Validation

A couple of years back at the Design Automation Conference (DAC), as I strolled through the exhibit floor, I couldn’t...
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