SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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Teaching the computers to teach themselves

Why Machine Learning Matters Machine learning (or “ML” for short) may have begun life as something of a buzzword, but...

What ARE the Root Causes of Functional Flaws?

By Louie de Luna, Agnisys Director of North American Sales and Marketing...

First sale is always sweet!

I’m thrilled. Finally, we have a customer who sees the value that IDesignSpec brings for his company. We are indeed...

IDS NextGen: SoC/IP Specification & Code Gen Tool | Agnisys

I’m yet to meet a person who doesn’t like simplicity in engineering. I do believe that   Electronic Design Automation (EDA)...

DVinsight: Universal Verification Methodology IDE at DAC Day 3

Ending the last day of DAC strong with a presentation of DVinsight, a Universal Verification Methodology IDE The highlight of...

Using IVerifySpec to test IDesignSpec

IDesignSpec generates several outputs from a single spec. We started out as a simple tool that just dealt with registers...

DAC Day 1: Universal Verification Methodology Adoption

The first day of the Design Automation Conference for Agnisys was exciting.  We experienced a higher traffic flow than Monday...
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