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DVCon Europe Needs Automatic Register Verification and Generation

DVCon Europe Needs Automatic Register Verification and Generation

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I feel like a bumblebee, going from the DVCon in US, to the next one in India to then to Europe.  All this cross-pollination is exciting and enriching when Bee and DVCON-Flowersexperiencing the needs of the Semiconductor design engineers across the globe and sharing our solutions with them.

IDesignSpec was a real hit at the DVCon Europe conference, not just because it helps engineers capture their register specifications and generate code for design, UVM verification, software engineers, but also because it also does so much more by automating the verification process for the registers as well.   It takes the complexity of managing and verifying registers off of the table. 

Our timing is great with the recent availability of Automatic Register Verification as a capability in the IDesignSpec Advanced product option.  With this capability, we have gone one step further by creating the entire register verification test bench environment automatically.  To see a brief demonstration video, please click on the link below. 

IDesignSpec Demonstration request

I got a first hand look at the UVM-SystemC working group status. I specifically asked for a release date for UVM-SystemC and received a tentative date of 2nd quarter of 2015.   Based on the demand I have seen, it cannot come soon enough!

DVCon-EuropeRequirement driven verification was the new catch phrase at DVCon. This is something we have been doing for almost three years now with our IDesignSpec product.

Another important topic at the event was UPF (The Unified Power Format – IEEE 1801-2009 the industry standard for design and verification of low power integrated circuits.)  This standard is seeing widespread adoption in a world where low power semiconductors are a requirement in the mobile phone and internet-of-things markets. 

20 advantages for automating your ASIC or FPGA transition from Specification to Design