SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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Smart Assembly of SoC Designs

Navigating SoC Complexity System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design...

Making Way For Register Specification Software

While more registers mean more functionality and configurability, more is not always better...

Correct-By-Construction SystemVerilog UVM Testbenches

Modern RTL design verification (DV) environments are both compelling and very complex. They include advanced simulation testbenches plus support for...

How To Create Complex Registers in IDesignSpec

We talk about the creation of complex registers in IDesignSpec and the generation of their suitable RTL and UVM models...

Agnisys | Next Generation of Register, Sequence, and SoC Automation

Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and...

Specification-Driven UVM Testbench Generation

In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM)...

Agnisys makes Design Verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry...

5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

Modern SoCs get more and more complicated every day.  As the complexity of modern electronic semiconductor device design increases, niche...
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