SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES
IDesignSpec generates several outputs from a single spec. We started out as a simple tool that just dealt with registers...
The first day of the Design Automation Conference for Agnisys was exciting. We experienced a higher traffic flow than Monday...
The input format of Duolog is now supported by IDesignSpec with outputs including Verilog, UVM, CHeader, and SystemC. The outputs generated...
1981 marked the beginning of EDA as an industry. Within a few years there were many companies specializing in EDA...
I admit it, I get a high when meeting customers and hearing how they are using our tools. It is...
Hardware design verification consumes more than 60% of resources, often more than that. These resources are not just engineers but...
San Francisco, CA. June 2nd, 2014 – Agnisys, Inc. Launches DVInsight™, an Integrated Development Environment (IDE) for creating SystemVerilog (SV)...
When engineers discuss system-on-chip (SoC) designs, they’re almost always talking about embedded systems with both hardware and software content. In...
In our first Newsletter of 2022 we are drawing your attention to new capabilities in the IDesignSpec family of products...
