Three Smart Steps to Quickly Test a Register Map for Your Entire SoC
As I noted in a recent post, registers appear everywhere in system-on-chip (SoC) design. Architecturally defined registers form the hardware-software […]
Register Verification
Electronic Design Automation Trade Show Update – 52DAC
Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher
Top 2018 Agnisys Resources
Every year we take a look back at the resources we’ve created to determine what you’ve found most useful. We
2015 Year End review – DV Challenges
Wow, what a marvelous year 2015 has been to Agnisys, full of events at the various technical exhibitions, new customers,
Creating Test Sequences for RISC-V Cores and SoCs
By Louie De Luna, Agnisys Chief Product Evangelist
Setting the Stage for the Next Abstraction
By Louie De Luna, Agnisys Chief Product Evangelist
Making Way For Register Specification Software
While more registers mean more functionality and configurability, more is not always better.
Not your Average UVM Testbench Generator – Unveiling at DAC 2019
By Louie De Luna, Agnisys Chief Product Evangelist
Integration is Key for the Adoption of Specification Automation
I frequently delve into the solutions Agnisys offers for the seamless generation of design, SoC verification, testing, software, validation, and
Where Tool Ideas Come From – A Case for a Portable Sequence Generator
By Louie De Luna, Agnisys Director of Sales and Marketing
Automatic Register Verification Gains Acceptance at DAC
With the Design Automation Conference wrapping up this week in San Francisco, there is one thing we can say
The Ultimate Shift Left
Important observations from Einstein and New England’s ice traders..
Musings from ARM TechCon Santa Clara 2015
The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but a few who were genuinely interested in
Repurposing von Neumann Architecture with SRAM-based Register File
By Louie De Luna, Agnisys Chief Product Evangelist
Register Automation using Machine Learning
By Louie De Luna, Agnisys Director of Sales and Marketing
News
Agnisys to Develop Next-Generation GDDR6 PHY IP for Six Semiconductor
BOSTON, MA – December 3, 2019 – Agnisys, Inc.® today announced that The Six Semiconductor Inc., an analog mixed-signal IP
News
Agnisys Announces Series of Webinars on Chip Specification Automation
Online events support remote learning, accommodating worldwide development teams with live sessions and on-demand replay BOSTON, Mass. – May 21,
