IDesignSpec^TM comprehensively manages register maps for complex designs. Engineers describe the register map and all derived views are automatically generated from it. Consistency checks are performed up-front before any output is generated so that errors are eliminated at the source. Even complex, hierarchical, multi-dimensional registers can be described easily and intuitively.

IAssertSpec^TM is a patent-pending technology purposefully built to ease the adoption of assertion based design and verification methodology. Quite simply, it aids the assertion developer to learn the new language paradigm quickly and ensure that the assertions are consistent with the requirement specification.