DVCon Europe Special Edition – Agnisys Spotlight 2018 | Agnisys
With DVCon Europe 2018 just around the corner, this special edition of the Agnisys Newsletter focuses its spotlight on the future. In this issue, we review several enhancements in design specification using IDesignSpec.
SystemRDL is a language used for the design and delivery of intellectual property (IP) products in design systems. SystemRDL semantics supports an entire life-cycle of registers right from the specification, model generation, and design verification, to maintenance and documentation. Registers are not just limited to traditional configuration but can also refer to register arrays and memory. Read More
RTL Wrapper in IDesignSpec
Complex hardware IP or SoC can have hundreds and thousands of configuration and status registers. An accurate memory map description and its interface to standard buses are needed by the design, verification, firmware, diagnostics, tech-pubs, and customers. With the designs getting more and more complex, often additional manual steps are required by the users in an otherwise fully automated specification to code the process. Uncertainty in the development process leads to a lot of time waste and productivity loss. Read More Non-encoding and broadcast in Indirect Index Register
IDesignSpec (IDS) enables users to create indirect registers. By default, an index register is decimal encoded. For instance, if the index register has value 101, then the 5+1=6th register in the memory or register array is written. But this does not serve the purpose. There is an urgent need for the non-encoded index registers with the capability to write and read multiple registers at the same time (multicast and broadcast). Read More
IDesignSpec NextGen – The current state of the art in Hardware Software Interface
IDS NextGen (IDS-NG) has been created as a new Integrated Development Environment (IDE), which enables users to capture the specification of IP and SoC at an enterprise level. IDS-NG is a multi-platform product and it deals with multiple format specifications such as Register view, Spreadsheet View, Sequence View, and Param View. It is not only capable of handling individual IP and sub-system but can also handle SoC level. Along with this, it is compatible with Word, Excel, IP-XACT, RALF, CSV and System RDL as input and output both. Read More